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| Direct RDRAM 128/144-MBit (256Kx16/18x32s) Overview The Rambus Direct RDRAMTM is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 128/144-Mbit Direct Rambus DRAMs (RDRAM(R)) are extremely high-speed CMOS DRAMs organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. The two data bits in the x18 organization are general and can be used for additional storage and bandwidth or for error correction. Features * Highest sustained bandwidth per DRAM device - 1.6 GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simultaneously at full bandwidth data rates * Low latency features - Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions * Advanced power management: - Multiple low power states allows flexibility in power consumption versus time to transition to active state - Power-down self-refresh * Organization: 1 Kbyte pages and 32 banks, x16/18 - x18 organization allows ECC configurations or increased storage/bandwidth - x16 organization for low cost applications * Uses Rambus Signaling Level (RSL) for up to 800 MHz operation * The ODF function is allready implemented in this device and will be described in a later version of this document INFINEON Technologies 1 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Figure 1 Direct RDRAM CSP Package The 128/144-Mbit Direct RDRAMs are offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAMs operate from a 2.5 V supply. Table 1 Key Timing Parameters/Part Numbers I/O Freq. MHz 600 711 800 800 600 711 800 800 600 711 800 800 600 711 800 800 Trac Part Number Organization Normal Package: 8M x 18 8M x 18 8M x 18 8M x 18 8M x 16 8M x 16 8M x 16 8M x 16 Mirror Package: 53 ns 45 ns 45 ns 40 ns 53 ns 45 n s 45 ns 40 ns 53 ns 45 ns 45 ns 40 ns 53 ns 45 n s 45 ns 40 ns HYB25R144180C-653 HYB25R144180C-745 HYB25R144180C-845 HYB25R144180C-840 HYB25R128160C-653 HYB25R128160C-745 HYB25R128160C-845 HYB25R128160C-840 HYB25M144180C-653 HYB25M144180C-745 HYB25M144180C-845 HYB25M144180C-840 HYB25M128160C-653 HYB25M128160C-745 HYB25M128160C-845 HYB25M128160C-840 8M x 18 8M x 18 8M x 18 8M x 18 8M x 16 8M x 16 8M x 16 8M x 16 INFINEON Technologies 2 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Pinouts and Definitions This tables show the pin assignments of the RDRAM package from the top-side of the package (the view looking down on the package as it is mounted on the circuit board). The mechanical dimensions of this package are shown in a later section. Refer to Section "Center-Bonded FBGA Package" on page 86. Note - pin #1 is at the A1 position. DQA8/DQB8 are used for 144 Mbit only. They are N.C. for 128Mbit. Table 2 12 11 10 9 8 7 6 5 4 3 2 1 Normal Package (top view) GND - - DQA4 VDD - - CFMN GNDa - - RQ5 - - RQ3 GND RQ2 VDD - - DQB4 GND - DQA7 GND CMD - CFM GND DQA2 - DQB0 - DQB7 GND SIO1 VDD DQA5 VDD RQ6 VDD DQB1 VDD DQB5 VDDa - - SCK - - DQA6 GND DQA3 - - DQA1 - - VREF GND CTMN - - RQ7 GND CTM - - RQ1 - - DQB2 GND RQ0 - - DQB6 GND DQB3 - - SIO0 VCMOS DQA8 VDD DQA0 VDD RQ4 VCMOS DQB8 - GND A - - B - VDD C - - D - - E - - F - VDD G - - H - GND J Table 3 12 11 10 9 8 7 6 5 4 3 2 1 Mirrored Package (top view) GND - - DQA3 GND DQA6 VDD - - CTMN GND - - CTM GND RQ7 - - RQ4 VDD - - DQB3 GND DQB6 GND - DQA8 - DQA0 - RQ0 GND DQB2 - DQB8 VCMOS SCK VDD DQA1 VDD RQ1 VCMOS SIO0 VREF - - CMD GND DQA7 - - DQA5 - - DQA2 GND CFM - - VDDa GNDa CFMN - - RQ6 - - RQ2 GND RQ3 - - DQB1 - - DQB5 - - SIO1 GND DQB7 VDD DQA4 VDD RQ5 VDD DQB0 VDD DQB4 - GND A - - B - VDD C - - D - - E - - F - VDD G - - H - GND J INFINEON Technologies 3 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 4 Signal SIO1,SIO0 I/O I/O Type CMOS1) # Pins # Pins Edge Center 2 2 Description Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. Serial clock input. Clock source used for reading from and writing to the control registers. Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. DQA8 is not used by RDRAMs with a x16 organization. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity Logic threshold reference voltage for RSL signals Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Row access control. Three pins containing control and address information for row accesses. Column access control. Five pins containing control and address information for column accesses. Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. DQB8 is not used by RDRAMs with a x16 organization. CMD I CMOS1) 1 1 SCK I CMOS1) 1 14 2 2 19 2 9 1 6 1 2 9 1 9 VDD VDDa VCMOS GND GNDa DQA8 ... DQA0 - - - - - I/O - - - - - RSL2) CFM CFMN I I RSL2) RSL2) 1 1 1 1 1 1 1 1 3 5 9 VREF CTMN CTM I I RSL 2) 1 1 3 5 9 RSL2) RSL2) RSL2) RSL2) RQ7 ... RQ5 or I ROW2 ... ROW0 RQ4 ... RQ0 or COL4 ... COL0 DQB8 ... DQB0 I I/O Total pin count per package 1) 2) 74 54 - All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero. INFINEON Technologies 4 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) DQB8...DQB0 9 RQ7...RQ5 or ROW2...ROW0 3 RCLK 1:8 Demux CTM CTMN SCK, CMD SIO0, SIO1 2 2 CFM CFMN RQ4...RQ0 or COL4...COL0 5 RCLK 1:8 Demux DQA8...DQA0 9 Packet Decode ROWR 11 5 5 BR ROWA 9 R TCLK Control Registers RCLK COLX 6 5 5 5 5 Packet Decode COLC 5 BC 6 C 8 MB COLM 8 MA ROPAV DR REFR Power Modes DEVID XOPM DX BX COPS DC Match DM Mux Row Decode PRER ACT Sense Amp 32 x 72 SAmp 0 Match XOP Decode Match Write Buffer Mux Mux 72 SAmp 0 Internal DQB Data Path DRAM Core 32 x 72 512 x 64 x 144 Bank 0 Column Decode & Mask PREX RD, WR 32 x 72 72 Internal DQA Data Path SAmp 0/1 Bank 1 SAmp 1/2 SAmp 1/2 9 RCLK 9 SAmp 0/1 9 9 RCLK Bank 2 Write Buffer Write Buffer 1:8 Demux 9 1:8 Demux 8:1 Mux 9 Bank 13 SAmp 13/14 SAmp 13/14 Bank 14 SAmp 14/15 SAmp 14/15 Bank 15 SAmp 15 SAmp 15 SAmp 16 9 SAmp 16/17 SAmp 16 Bank 16 SAmp 16/17 9 TCLK TCLK Bank 17 SAmp 17/18 SAmp 17/18 9 8:1 Mux Bank 18 9 Bank 29 SAmp 29/30 SAmp 29/30 Bank 30 SAmp 30/31 SAmp 30/31 Bank 31 SAmp 31 SAmp 31 SPB04206 Figure 2 128/144-MBit Direct RDRAM Block Diagram INFINEON Technologies 5 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) General Description Figure 2 is a block diagram of the 128/144 Mbit Direct RDRAM. It consists of two major blocks: a "core" block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6 GB/s. Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of Figure 2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From-Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. DQA, DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed/de-multiplexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM. Banks: The 16 Mbyte core of the RDRAM is divided into 32 0.5 Mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed. Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 512 bytes of fast storage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 30, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed. RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7 ... RQ5 are also called ROW2 ... ROW0, and are used primarily for controlling row accesses. RQ4 ... RQ0 are also called COL4 ... COL0, and are used primarily for controlling column accesses. ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated. INFINEON Technologies 6 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) RD Command: The RD (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround. PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M = 0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge. Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 5 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM. The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the "RsvX" notation to reserve bits for future address field extension. Table 5 Field DR4T, DR4F DR3 ... DR0 BR4 ... BR0 AV R8 ... R0 Field Description for ROWA Packet and ROWR Packet Description Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. Device address for ROWA or ROWR packet. Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM. Selects between ROWA packet (AV = 1) and ROWR packet (AV = 0). Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM. ROP10 ... ROP0 Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions. Figure 3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 6 describes the fields which comprise these packets. INFINEON Technologies 7 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands. The remaining 17 bits are interpreted as a COLM (M = 1) or COLX (M = 0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time tRTR earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet. Table 6 Field S DC4 ... DC0 BC4 ... BC0 C5 ... C0 COP3 ... COP0 M MA7 ... MA0 MB7 ... MB0 DX4 ... DX0 BX4 ... BX0 XOP4 ... XOP0 Field Description for COLC Packet, COLM Packet, and COLX Packet Description Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. Device address for COLC packet. Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0's). Column address for COLC packet. RsvC denotes bits ignored by the RDRAM. Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. Selects between COLM packet (M = 1) and COLX packet (M = 0). Bytemask write control bits. 1 = write, 0 = no-write. MA0 controls the earliest byte on DQA8 ... 0. Bytemask write control bits. 1 = write, 0 = no-write. MB0 controls the earliest byte on DQB8 ... 0. Device address for COLX packet. Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0's). Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions. INFINEON Technologies 8 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) ROWA Packet T0 CTM/CFM ROW2 ROW1 ROW0 DR4T DR2 BR0 BR3 RsvR R8 R5 R2 ROWR Packet T3 CTM/CFM ROW2 ROW1 ROW0 DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5 ROP2 T1 T2 T8 T9 T10 T11 DR4F DR1 BR1 BR4 RsvR R7 R4 R1 DR4F DR1 BR1 4RsvB ROP9 ROP7 ROP4 ROP1 DR3 DR0 BR2 RsvB AV=1 R6 R3 R0 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0 COLC Packet T0 CTM/CFM COL4 COL3 COL2 COL1 COL0 DC4 S = 1 RsvC C4 T1 T2 T3 CTM/CFM ROW2...ROW0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 ACT a0 PRER c0 t Packet DC3 C5 C3 COL4...COL0 DC2 COP1 RsvB BC2 C2 WR b1 MSK (b1) PREX (d0) DC1 COP0 BC4 BC1 C1 DQA8...0 DQB8...0 DC0 COP2 COP3 BC3 BC0 C0 COLM Packet T8 CTM/CFM COL4 COL3 COL2 COL1 COL0 a) COLX Packet T11 CTM/CFM T12 T13 T14 T15 T9 T10 S=1a MA7 MA5 MA3 MA1 COL4 COL3 COL2 COL1 COL0 b) S=1b DX4 XOP4 RsvB BX1 M = 1 MA6 MA4 MA2 MA0 M = 0 DX3 XOP3 BX4 BX0 MB7 MB4 MB1 DX2 XOP2 BX3 MB6 MB3 MB0 DX1 XOP1 BX2 MB5 MB2 DX0 XOP0 The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S = 1) position. The COLX is aligned with the present COLC, indicated by the Start bit (S = 1) position. SPB04207 Figure 3 Packet Formats 9 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) Field Encoding Summary Table 7 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed. Table 7 Device Field Encodings for ROWA Packet and ROWR Packet Device Match Signal (DM) DM is set to 1 if {DEVID4 ... DEVID0} == {0, DR3 ... DR0} else DM is set to 0 DM is set to 1 if {DEVID4 ... DEVID0} == {1, DR3 ... DR0} else DM is set to 0 DM is set to 0 DR4T DR4F Device Selection 1 0 1 0 1 1 0 0 One device selected One device selected No packet present All devices (broadcast) DM is set to 1 Table 8 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refreshprecharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in "Power State Management" on page 58. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in "Current and Temperature Control" on page 65. INFINEON Technologies 10 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 8 DM 1) ROWA Packet and ROWR Packet Field Encodings ROP10...ROP0 Field 10 9 8 7 6 5 4 3 2:0 --ACT 0 1 x3) x 0 0 x x 000 PRER 000 REFA No operation. Activate row R8 ... R0 of bank BR4 ... BR0 of device and move device to ATTN2). Precharge bank BR4 ... BR0 of this device. Refresh (activate) row REFR8 ... REFR0 of bank BR3 ... BR0 of device. Increment REFR if BR4 ... BR0 = 1111 (see Figure 50). Precharge bank BR4 ... BR0 of this device after REFA (see Figure 50). Move this device into the powerdown (PDN) power state (see Figure 47). Move this device into the nap (NAP) power state (see Figure 47). Name Command Description AV 0 1 1 1 1 0 0 Row address 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1) 0 0 0 0 0 0 0 0 0 1 x x x x x 0 0 0 0 x x x x x 0 0 0 1 0 0 0 x x 0 0 0 0 0 0 0 x x 0 0 0 1 0 0 0 x x 0 0 0 0 0 1 1 x x 0 0 0 0 1 0 1 x x 0 0 0 x x x x 0 1 x x 0 000 REFP 000 PDNR 000 NAPR 000 NAPRC Move this device into the nap (NAP) power state conditionally. 000 ATTN2) 000 RLXR 001 TCAL 010 TCEN Move this device into the attention (ATTN) power state (see Figure 45). Move this device into the standby (STBY) power state (see Figure 46). Temperature calibrate this device (see Figure 52). Temperature calibrate/enable this device (see Figure 52). 000 NOROP No operation. 2) 3) The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3 ... DR0 field of the ROWA and ROWR packets. See Table 7. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F = 1/1). An "x" entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000). Table 9 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 17 for a more detailed description. The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See "Power State Management" on page 58. INFINEON Technologies 11 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 9 S 0 1 1 1 COLC Packet Field Encodings COP3 ... 0 Name --------x000 2) DC4 ... DC0 (select device)1) ---/= (DEVID4 ... 0) == (DEVID4 ... 0) Command Description No operation. Retire write buffer of this device. Retire write buffer of this device, then write column C5 ... C0 of bank BC4 ... BC0 to write buffer. Reserved, no operation. Read column C5 ... C0 of bank BC4 ... BC0 of this device. Retire write buffer of this device, then precharge bank BC4 ... BC0 (see Figure 14). Same as WR, but precharge bank BC4 ... BC0 after write buffer (with new data) is retired. Reserved, no operation. Same as RD, but precharge bank BC4 ... BC0 afterward. Move this device into the standby (STBY) power state (see Figure 46). - - WR NOCOP Retire write buffer of this device. == (DEVID4 ... 0) x001 1 1 1 1 1 1 1 1) 2) == (DEVID4 ... 0) == (DEVID4 ... 0) == (DEVID4 ... 0) == (DEVID4 ... 0) == (DEVID4 ... 0) == (DEVID4 ... 0) == (DEVID4 ... 0) x010 x011 x100 x101 x110 x111 1xxx RSRV RD PREC WRA RSRV RDA RLXC "/=" means not equal, "==" means equal. An "x" entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001). INFINEON Technologies 12 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 10 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL (calibrate) and SAM (sample) current control commands (see "Current and Temperature Control" on page 65), and for the RLXX power mode command (see "Power State Management" on page 58). Table 10 COLM Packet and COLX Packet Field Encodings M 1 0 0 0 0 0 0 0 1) DX4 ... DX0 (selects device) ---/= (DEVID4 ... 0) XOP4 ... 0 - - Name MSK - NOXOP PREX CAL Command Description MB/MA bytemasks used by WR/WRA. No operation. No operation. Precharge bank BX4 ... BX0 of this device (see Figure 14). Calibrate (drive) IOL current for this device (see Figure 51). == (DEVID4 ... 0) 00000 == (DEVID4 ... 0) 1xxx01) == (DEVID4 ... 0) x10x0 == (DEVID4 ... 0) x11x0 == (DEVID4 ... 0) xxx10 == (DEVID4 ... 0) xxxx1 CAL/SAM Calibrate (drive) and Sample (update) IOL current for this device (see Figure 51). RLXX RSRV Move this device into the standby (STBY) power state (see Figure 46). Reserved, no operation. An "x" entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010). INFINEON Technologies 13 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) DQ Packet Timing Figure 4 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point. An RD or RDA command will transmit a dualoct of read data Q a time tCAC later. This time includes one to five cycles of round-trip propagation delay on the Channel. The tCAC parameter may be programmed to a one of a range of values (7, 8, 9, 10, 11, or 12 tCYCLE). The value chosen depends upon the number of RDRAM devices on the Channel and the RDRAM timing bin. See Figure 39 for more information. A WR or WRA command will receive a dualoct of write data D a time tCWD later. This time does not need to include the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction. When a Q packet follows a D packet (shown in the left half of the figure), a gap (tCAC - tCWD) will automatically appear between them because the tCWD value is always less than the tCAC value. There will be no gap between the two COLC packets with the WR and RD commands which schedule the D and Q packets. When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the tCWD value is less than the tCAC value. However, a gap of tCAC - tCWD or greater must be inserted between the COLC packets with the RD WR commands by the controller so the Q and D packets do not overlap. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM This gap on the DQA/DQB pins appears automatically This gap on the COL pins must be inserted by the controller ROW2... ROW0 t CAC - t CWD t CWD t CAC - t CWD WR d1 RD c1 COL4...COL0 WR a1 RD b1 t CWD t CAC Q (b1) t CAC Q (c1) D (d1) DQA8...0 DQB8...0 Q (y1) SPA04208 Figure 4 Read (Q) and Write (D) Data Packet - Timing for tCAC = 7, 8, 9, 10, 11, or 12 tCYCLE 14 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) COLM Packet to D Packet Mapping Figure 5 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is transmitted on the COL pins a time tRTR after the COLC packet containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure 17 for more details. If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (tRTR after the COLC packet) is available to be used as an COLX packet. This could be used for a PREX precharge command or for a housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits). Figure 5 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (= 1) or not written (= 0). INFINEON Technologies 15 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 ACT a0 PRER a2 ACT b0 t RTR COL4...COL0 WR a1 retire (a1) MSK (a1) t CWD DQA8...0 DQB8...0 Transaction a: WR a0 = {Da, Ba, Ra} D (a1) a1 = {Da, Ba, Ca1} a3 = {Da, Ba} D Packet COLM Packet T17 CTM/CFM T18 T19 T20 CTM/CFM T19 T20 T21 T22 COL4 COL3 COL2 COL1 COL0 MA7 MA5 MA3 MA1 DQB8 DQB7 DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB71 M = 1 MA6 MA4 MA2 MA0 DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70 MB7 MB4 MB1 MB6 MB3 MB0 DQB1 DQB0 DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64 MB5 MB2 DB0 MB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63 MB1 MB2 MB3 MB4 MB5 MB6 MB7 Each bit of the MB7...MB0 field controls writing (= 1) or no writing (= 0) of the indicated DB bits when the M bit of the COLM packet is one. DQA8 DQA7 When M = 1, the MA and MB fields control writing of individual data bytes. When M = 0, all data bytes are writing unconditionally. Each bit of the MA7...MA0 field controls writing (= 1) or no writing (= 0) of the indicated DA bits when the M bit of the COLM packet is one. DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA71 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70 DQA1 DQA0 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64 DA0 MA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63 MA1 MA2 MA3 MA4 MA5 MA6 MA7 SPA04209 Figure 5 Mapping Between COLM Packet and D Packet for WR Command 16 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) ROW-to-ROW Packet Interaction T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM t RRDELAY ROW2... ROW0 COL4...COL0 DQA8...0 DQB8...0 Transaction a: ROPa Transaction b: ROPb a0 = {Da, Ba, Ra} b0 = {Db, Bb, Rb} SPT04210 ROPa a0 ROPb b0 Figure 6 ROW-to-ROW Packet Interaction-Timing Figure 6 shows two packets on the ROW pins separated by an interval tRRDELAY which depends upon the packet contents. No other ROW packets are sent to banks {Ba, Ba+1, Ba-1} between packet "a" and packet "b" unless noted otherwise. Table 11 summarizes the tRRDELAY values for all possible cases. Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the tRR restriction applies to the same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted, tRRDELAY is tRC (tRAS to the PRER command, and tRP to the next ACT). Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the tRAS restriction means the activated bank must wait before it can be precharged. Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba 1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait tRP for the sense amp and bank to precharge before being activated. INFINEON Technologies 17 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 11 ROW-to-ROW Packet Interaction - Rules Case # ROPa Da Ba Ra ROPb Db RR1 RR2 RR3 RR4 RR5 RR6 RR7 RR8 RR9 RR10 ACT ACT ACT ACT ACT ACT ACT ACT Da Ba Da Ba Da Ba Da Ba Da Ba Da Ba Da Ba Da Ba Ra ACT Ra ACT Ra ACT Ra ACT /= Da Bb xxxx Rb tRRDELAY Example Figure 11 Figure 11 x...x tPACKET == Da /= {Ba, Ba+1, Ba-1} x...x tRR == Da == {Ba+1, Ba-1} == Da == {Ba} xxxx x...x tRC - illegal unless Figure 10 PRER to Ba/Ba+1/Ba-1 x...x tRC - illegal unless Figure 10 PRER to Ba/Ba+1/Ba-1 x...x tPACKET x...x tRAS x...x tRAS x...x tPACKET x...x tPACKET x...x tPACKET/tRP if Ba+1 is precharged/activated. x...x tPACKET/tRP if Ba-1 is precharged/activated. x...x tRP x...x tRP x...x tPACKET x...x tPP x...x tPP Figure 11 Figure 11 Figure 10 Figure 15 Figure 12 Figure 12 - - Figure 10 Figure 10 Figure 12 Figure 12 Figure 12 Figure 12 Ra PRER /= Da Ra PRER == Da /= {Ba, Ba+1, Ba-1} x...x tPACKET Ra PRER == Da == {Ba+1, Ba-1} Ra PRER == Da == {Ba} Ra ACT Ra ACT Ra ACT Ra ACT Ra ACT Ra ACT /= Da xxxx PRER Da Ba PRER Da Ba == Da /= {Ba, Ba1, Ba2} == Da == {Ba+2} == Da == {Ba-2} == Da == {Ba+1, Ba-1} == Da == {Ba} xxxx RR10a PRER Da Ba RR10b PRER Da Ba RR11 RR12 RR13 RR14 RR15 RR16 PRER Da Ba PRER Da Ba PRER Da Ba PRER Da Ba PRER Da Ba PRER Da Ba Ra PRER /= Da Ra PRER == Da /= {Ba, Ba+1, Ba-1} x...x tPP Ra PRER == Da == {Ba+1, Ba-1} Ra PRER == Da == Ba ROW-to-ROW Interaction (cont'd) Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, tPP applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the tPP restriction. Two adjacent banks can't be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later sections (see Table 8 for cross-ref). INFINEON Technologies 18 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) ROW-to-COL Packet Interaction Figure 7 shows two packets on the ROW and COL pins. They must be separated by an interval tRCDELAY which depends upon the packet contents. Table 12 summarizes the tRCDELAY values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a COL-to-ROW packet interaction. Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure 15 and Figure 16 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM t RCDELAY ROW2... ROW0 COL4...COL0 DQA8...0 DQB8...0 Transaction a: ROPa a0 = {Da, Ba, Ra} Transaction b: COPb b1 = {Db, Bb, Cb1} SPT04211 ROPa a0 COPb b1 Figure 7 ROW-to-COL Packet Interaction - Timing Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9). The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in Figure 14. INFINEON Technologies 19 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 12 ROW-to-COL Packet Interaction - Rules Case # RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 ROPa ACT ACT ACT ACT ACT PRER PRER PRER PRER Da Da Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra COPb NOCOP, RD, retire NOCOP RD, retire RD, retire RD, retire NOCOP, RD, retire NOCOP RD, retire RD, retire Db /= Da == Da == Da == Da == Da /= Da == Da == Da == Da Bb xxxx xxxx /= {Ba, Ba+1, Ba-1} == {Ba+1, Ba-1} == Ba xxxx xxxx /= {Ba, Ba+1, Ba-1} == {Ba+1, Ba-1} Cb1 x...x x...x x...x x...x x...x x...x x...x x...x x...x tRCDELAY 0 0 0 Illegal Example - - - - Figure 15 - - - - tRCD 0 0 0 Illegal COL-to-COL Packet Interaction T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM ROW2... ROW0 t CCDELAY COL4...COL0 DQA8...0 DQB8...0 Transaction a: COPa a1 = {Da, Ba, Ca1} Transaction b: COPb b1 = {Db, Bb, Cb1} Transaction c: COPc c1 = {Dc, Bc, Cc1} SPT04212 COPa a1 COPb b1 COPc c1 Figure 8 COL-to-COL Packet Interaction-Timing Figure 8 shows three arbitrary packets on the COL pins. Packets "b" and "c" must be separated by an interval tCCDELAY which depends upon the command and address values in all three packets. Table 13 summarizes the tCCDELAY values for all possible cases. Cases CC1 through CC5 summarize the rules for every situation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of tCAC - tCWD must be inserted between the two COL packets. See Figure 4 for more explanation of why this gap is needed. For cases CC1, CC2, CC4, and CC5, there is no restriction (tCCDELAY is tCC). INFINEON Technologies 20 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The tCCDELAY value needed between these two packets depends upon the command and address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure 18 (right) provides a more detailed explanation of this case. In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is unretired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Cases CC7, CC8, and CC9 have no restriction (tCCDELAY is tCC). For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 14. Table 13 COL-to-COL Packet Interaction - Rules Case # CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 COPa xxxx xxxx xxxx xxxx xxxx WR WR WR NOCOP RD Da xxxxx xxxxx xxxxx xxxxx xxxxx == Db == Db /= Db == Db == Db Ba Ca1 COPb Db Db Db Db Db Db Db Db Db Db Db Bb Bb Bb Bb Bb Bb Bb Bb Bb Bb Bb Cb1 COPc Cb1 xxxx Dc xxxxx Bc x...x x...x x...x x...x x...x x...x x...x x...x x...x x...x Cc1 tCCDELAY x...x tCC x...x tCC Example - - x...x x...x NOCOP x...x x...x RD,WR x...x x...x RD x...x x...x RD x...x x...x WR x x x x x x...x WR x...x WR x...x WR x...x WR x...x WR Cb1 NOCOP xxxxx Cb1 WR Cb1 RD Cb1 WR Cb1 RD Cb1 RD Cb1 RD Cb1 RD Cb1 RD xxxxx xxxxx xxxxx == Db /= Db == Db == Db == Db x...x tCC +tCAC-tCWD Figure 4 x...x tCC x...x tCC x...x tRTR x...x tCC x...x tCC x...x tCC x...x tCC Figure 15 Figure 16 Figure 18 - - - - INFINEON Technologies 21 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) COL-to-ROW Packet Interaction T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM t CRDELAY ROW2... ROW0 COL4...COL0 DQA8...0 DQB8...0 Transaction a: COPa a1 = {Da, Ba, Ca1} Transaction b: ROPb b0 = {Db, Bb, Rb} SPT04213 ROPb b0 COPa a1 Figure 9 COL-to-ROW Packet Interaction - Timing Figure 9 shows arbitrary packets on the COL and ROW pins. They must be separated by an interval tCRDELAY which depends upon the command and address values in the packets. Table 14 summarizes the tCRDELAY value for all possible cases. Cases CR1, CR2, CR3, and CR9 show no interaction between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks. Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged Case CR5 is illegal because an adjacent bank can't be activated or precharged until bank Ba is precharged first. In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The tRDP parameter specifies the required spacing. Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a PRER command for the same bank. The tRTP parameter specifies the required spacing. Case CR8 is labeled "Hazardous" because a WR command should always be followed by an automatic retire before a precharge is scheduled. Figure 19 shows an example of what can happen when the retire is not able to happen before the precharge. For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 14. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR commands are discussed in a later section. INFINEON Technologies 22 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 14 COL-to-ROW Packet Interaction - Rules Case # CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 1) COPa NOCOP RD/WR RD/WR RD/WR RD/WR RD retire WR 2) 1) Da Da Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 ROPb x...x x...x x...x ACT ACT PRER PRER PRER NOROP Db xxxxx /= Da == Da == Da == Da == Da == Da == Da xxxxx Bb xxxx xxxx /= {Ba, Ba+1, Ba-1} == {Ba} == {Ba+1, Ba-1} == {Ba, Ba+1, Ba-1} == {Ba, Ba+1, Ba-1} == {Ba, Ba+1, Ba-1} xxxx Rb x...x x...x x...x x...x x...x x...x x...x x...x x...x tCRDELAY 0 0 0 Illegal Illegal Example - - - - - Figure 15 Figure 16 Figure 19 - tRDP tRTP 0 0 xxxx 2) This is any command which permits the write buffer of device Da to retire (see Table 9). "Ba" is the bank address in the write buffer. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19. INFINEON Technologies 23 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) ROW-to-ROW Examples Figure 10 shows examples of some of the ROW-to-ROW packet spacings from Table 11. A complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the tRAS and tRP timing parameters, the separation between ACT commands to the same bank must also satisfy the tRC timing parameter (RR4). When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules are analogous to the RR12 and RR4 rules. Same Device Same Device Same Device Same Device Same Device Adjacent Bank RR7 Adjacent Bank RR3 Same Bank RR4 Adjacent Bank RR11 Same Bank RR12 a0 = {Da, Ba, Ra} a1 = {Da, Ba+1} b0 = {Da, Ba+1, Rb} b0 = {Da, Ba, Rb} b0 = {Da, Ba+1, Rb} b0 = {Da, Ba, Rb} T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 ACT a0 PRER a1 ACT b0 t RAS COL4...COL0 t RP t RC DQA8...0 DQB8...0 SPA04214 Figure 10 Row Packet Example Figure 11 shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6) command spacings from Table 11. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. INFINEON Technologies 24 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Any Bank Different Device Same Device Non-adjacent Bank Different Device Any Bank Same Device Non-adjacent Bank T0 T1 T2 T3 T4 T5 T6 T7 T8 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 RR1 RR2 RR5 RR6 a0 = {Da, Ba, Ra} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} T39 T40 T41 T42 T43 T44 T45 T46 T47 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 CTM/CFM ROW2... ROW0 ACT a0 ACT b0 ACT a0 ACT c0 ACT a0 PRER b0 ACT a0 PRER c0 t PACKET COL4...COL0 t RR t PACKET t PACKET DQA8...0 DQB8...0 SPA04215 Figure 11 Row Packet Example Figure 12 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table 12. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. INFINEON Technologies 25 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Different Device Any Bank Same Device Non-adjacent Bank Same Device Adjacent Bank Same Bank Same Device Any Bank Different Device Same Device Non-adjacent Bank T0 T1 T2 T3 T4 T5 T6 T7 T8 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 RR13 RR14 RR15 RR16 RR9 RR10 a0 = {Da, Ba, Ra} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} c0 = {Da, Ba, Rc} c0 = {Da, Ba+1, Rc} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} T39 T40 T41 T42 T43 T44 T45 T46 T47 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 CTM/CFM ROW2... ROW0 PRER a0 PRER b0 PRER a0 PRER c0 PRER a0 ACT b0 PRER a0 ACT c0 t PACKET COL4...COL0 t PP t PACKET t PACKET DQA8...0 DQB8...0 SPA04216 Figure 12 Row Packet Examples Row and Column Cycle Description Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of sensing the value of a bit in a bank's storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation. Intervals: The activate operation requires the interval tRCD,MIN to complete. The hidden restore operation requires the interval tRAS,MIN - tRCD,MIN to complete. Column read and write operations are also performed during the tRAS,MIN - tRCD,MIN interval (if more than about four column operations are INFINEON Technologies 26 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) performed, this interval must be increased). The precharge operation requires the interval tRP,MIN to complete. Adjacent Banks: An RDRAM with a "s" designation (256K x 32s x 16/18) indicates it contains "split banks". This means the sense amps are shared between two adjacent banks. The only exception is that sense amp 0, 15, 30, and 31 are not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. For example (referring to the block diagram of Figure 2), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 1 Kbyte row - 256 bytes to the DQA side and 256 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing. Precharge Mechanisms Figure 13 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time tRAS after the ACT command, and a time tRP before the next ACT command. This timing will serve as a baseline against which the other precharge mechanisms can be compared. a0 = {Da, Ba, Ra} a5 = {Da, Ba} b0 = {Da, Ba, Rb} T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 ACT a0 PRER a5 ACT b0 t RAS COL4...COL0 t RP t RC DQA8...0 DQB8...0 SPA04217 Figure 13 Precharge via PRER Command in ROWR Packet Figure 14 (top) shows an example of precharge with a RDA command. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank to automatically precharge when the final read has finished. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP INFINEON Technologies 27 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) from the COLC packet with the RDA command. The RDA command should be treated as a RD command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Figure 14 (middle) shows an example of precharge with a WRA command. As in the RDA example, a bank is activated with an ROWA packet on the ROW pins. Then, two dualocts are written with WR commands in COLC packets on the COL pins. The second of these commands is a WRA, which causes the bank to automatically precharge when the final write has been retired. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLC packet that causes the automatic retire. The WRA command should be treated as a WR command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Note that the automatic retire is triggered by a COLC packet a time tRTR after the COLC packet with the WR command unless the second COLC contains a RD command to the same device. This is described in more detail in Figure 17. Figure 14 (bottom) shows an example of precharge with a PREX command in an COLX packet. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these COLC packets includes an COLX packet with a PREX command. This causes the bank to precharge with timing equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLX packet with the PREX command. INFINEON Technologies 28 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) COLC Packet: RDA Precharge Offset T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM The RDA precharge is equivalent to a PRER command here ROW2... ROW0 ACT a0 PRER a5 ACT b0 t OFFP COL4...COL0 DQA8...0 DQB8...0 Transaction a: RD a0 = {Da, Ba, Ra} RD a1 RD a2 RD a3 RD a4 Q (a1) Q (a2) Q (a3) Q (a4) a1 = {Da, Ba, Ca1} a3 = {Da, Ba, Ca3} a2 = {Da, Ba, Ca2} a4 = {Da, Ba, Ca4} a5 = {Da, Ba} COLC Packet: WRA Precharge Offset T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here ROW2... ROW0 ACT a0 PRER a5 ACT b0 t RTR COL4...COL0 DQA8...0 DQB8...0 Transaction a: WR a0 = {Da, Ba, Ra} WR a1 WRA a2 retire (a1) retire (a2) MSK (a1) MSK (a2) t OFFP D (a1) D (a2) a1 = {Da, Ba, Ca1} a2 = {Da, Ba, Ca2} a5 = {Da, Ba} COLC Packet: PREX Precharge Offset T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM The PREX precharge is equivalent to a PRER command here ROW2... ROW0 ACT a0 PRER a5 ACT b0 t OFFP COL4...COL0 DQA8...0 DQB8...0 Transaction a: RD a0 = {Da, Ba, Ra} RD a1 RD a2 RD a3 RD a4 PREX a5 Q (a1) Q (a2) Q (a3) Q (a4) a1 = {Da, Ba, Ca1} a3 = {Da, Ba, Ca3} a2 = {Da, Ba, Ca2} a4 = {Da, Ba, Ca4} a5 = {Da, Ba} SPA04218 Figure 14 Offsets for Alternate Precharge Mechanisms 29 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) Read Transaction - Example Figure 15 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time tRCD later a RD a1 command is issued in a COLC packet. Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and column address (abbreviated as a1). A time tCAC after the RD command the read data dualoct Q(a1) is returned by the device. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time tCC after the first COLC packet on the COL pins a second is issued. It contains a RD a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time tCAC after the second RD command a second read data dualoct Q(a2) is returned by the device. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time tRAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the tRAS interval). The PRER command must also occur a time tRDP or more after the last RD command. Note that the tRDP value shown is greater than the tRDP,MIN specification in Table 23. This transaction example reads two dualocts, but there is actually enough time to read three dualocts before tRDP becomes the limiting parameter rather than tRAS. If four dualocts were read, the packet with PRER would need to shift right (be delayed) by one tCYCLE (note - this case is not shown). Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time tRC or more after the first ACT command and a time tRP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a INFINEON Technologies 30 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RC ROW2... ROW0 ACT a0 PRER a3 ACT b0 t RAS COL4...COL0 RD a1 RD a2 t CC t RCD t CAC DQA8...0 DQB8...0 Transaction a: RD Transaction b: XX a0 = {Da, Ba, Ra} b0 = {Da, Ba, Rb} t CAC t RDP Q (a1) Q (a2) a1 = {Da, Ba, Ca1} a2 = {Da, Ba, Ca2} a3 = {Da, Ba} SPT04219 Figure 15 Read Transaction Example Write Transaction - Example Figure 16 shows an example of a write transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time tRCD - tRTR later a WR a1 command is issued in a COLC packet (note that the tRCD interval is measured to the end of the COLC packet with the first retire command). Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the WR command includes device, bank, and column address (abbreviated as a1). A time tCWD after the WR command the write data dualoct D(a1) is issued. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time tCC after the first COLC packet on the COL pins a second COLC packet is issued. It contains a WR a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time tCWD after the second WR command a second write data dualoct D(a2) is issued. A time tRTR after each WR command an optional COLM packet MSK (a1) is issued, and at the same time a COLC packet is issued causing the write buffer to automatically retire. See Figure 17 for more detail on the write/retire mechanism. If a COLM packet is not used, all data bytes are unconditionally written. If the COLC packet which causes the write buffer to retire is delayed, then the COLM packet (if used) must also be delayed. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time tRAS or more after the original INFINEON Technologies 31 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the tRAS interval). A PRER a3 command is issued in an ROWR packet on the ROW pins. The PRER command must occur a time tRTP or more after the last COLC which causes an automatic retire. Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time tRC or more after the first ACT command and a time tRP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RC t RAS ROW2... ROW0 ACT a0 PRER a3 t RP ACT b0 t RCD t RTR t RTR COL4...COL0 WR a1 WR a2 retire (a1) retire (a2) MSK (a1) MSK (a2) t RTP t CC t CWD DQA8...0 DQB8...0 Transaction a: WR Transaction b: XX a0 = {Da, Ba, Ra} b0 = {Da, Ba, Rb} t CWD D (a1) D (a2) a1 = {Da, Ba, Ca1} a2 = {Da, Ba, Ca2} a3 = {Da, Ba} SPT04220 Figure 16 Write Transaction Example INFINEON Technologies 32 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Write/Retire - Examples The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of transporting the write command, write address, and write data into the write buffer. The second step happens when the RDRAM automatically retires the write buffer (with an optional bytemask) into the sense amp. This two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. Figure 17 (left) shows an example of this two step process. The first COLC packet contains the WR command and an address specifying device, bank and column. The write data dualoct follows a time tCWD later. This information is loaded into the write buffer of the specified device. The COLC packet which follows a time tRTR later will retire the write buffer. The retire will happen automatically unless (1) a COLC packet is not framed (no COLC packet is present and the S bit is zero), or (2) the COLC packet contains a RD command to the same device. If the retire does not take place at time tRTR after the original WR command, then the device continues to frame COLC packets, looking for the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM packet aligned with the COLC that retires the write buffer at time tRTR after the WR command. The memory controller must be aware of this two-step write/retire process. Controller performance can be improved, but only if the controller design accounts for several side effects. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CTM/CFM Retire is automatic here unless: (1) No COLC packet (S = 0) or (2) COLC packet is RD to device Da CTM/CFM This RD gets the old data This RD gets the new data ROW2... ROW0 COL4... COL0 WR a1 retire (a1) MSK (a1) ROW2... ROW0 t CAC COL4... COL0 WR a1 RD b1 retire (a1) MSK (a1) RD c1 t CAC t RTR t CWD DQA8...0 DQB8...0 Transaction a: WR D (a1) t RTR t CWD DQA8...0 DQB8...0 Transaction a: WR Transaction b: RD Transaction c: RD D (a1) Q (b1) Q( a1 = {Da, Ba, Ca1} a1 = {Da, Ba, Ca1} b1 = {Da, Ba, Ca1} c1 = {Da, Ba, Ca1} SPT04221 Figure 17 Normal Retire (left) and Retire/Read Ordering (right) Figure 17 (right) shows the first of these side effects. The first COLC packet has a WR command which loads the address and data into the write buffer. The third COLC causes an automatic retire of the write buffer to the sense amp. The second and fourth COLC packets (which bracket the retire packet) contain RD commands with the same device, bank and column address as the original WR command. In other words, the same dualoct address that is written is read both before and after it is actually retired. The first RD returns the old dualoct value from the sense amp before it is overwritten. The second RD returns the new dualoct value that was just written. INFINEON Technologies 33 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Figure 18 (left) shows the result of performing a RD command to the same device in the same COLC packet slot that would normally be used for the retire operation. The read may be to any bank and column address; all that matters is that it is to the same device as the WR command. The retire operation and MSK(a1) will be delayed by a time tPACKET as a result. If the RD command used the same bank and column address as the WR command, the old data from the sense amp would be returned. If many RD commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to another device or a WR or NOCOP to any device is issued, the retire will take place. Figure 18 (right) illustrates a situation in which the controller wants to issue a WR-WR-RD COLC packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1) in the write buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued in the third COLC packet. Therefore, it is required in this situation that the controller issue a NOCOP command in the third COLC packet, delaying the RD command by a time of tPACKET. This situation is explicitly shown in Table 13 for the cases in which tCCDELAY is equal to tRTR . T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 CTM/CFM The retire operation for a write can be held off by a read to the same device CTM/CFM The controller must insert a NOCOP to retire (a1) to make room for the data (b1) in the write buffer ROW2... ROW0 ROW2... ROW0 t CAC COL4... COL0 WR a1 RD b1 retire (a1) MSK (a1) t CAC COL4... COL0 WR a1 WR b1 retire (a1) MSK (a1) RD c1 t RTR + t PACKET t CWD DQA8...0 DQB8...0 Transaction a: WR Transaction b: RD D (a1) Q t RTR t CWD DQA8...0 DQB8...0 Transaction a: WR Transaction b: WR Transaction c: RD D (a1) D (b1) a1 = {Da, Ba, Ca1} b1 = {Da, Bb, Cb1} a1 = {Da, Ba, Ca1} b1 = {Da, Bb, Cb1} c1 = {Da, Bc, Cc1} SPA04222 Figure 18 Retire Held Off by Read (left) and Controller Forces WWR Gap (right) Figure 19 shows a possible result when a retire is held off for a long time (an extended version of Figure 18-left). After a WR command, a series of six RD commands are issued to the same device (but to any combination of bank and column addresses). In the meantime, the bank Ba to which the WR command was originally directed is precharged, and a different row Rc is activated. When the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. The controller can insure that this doesn't happen by never precharging a bank with an unretired write buffer. Note that in a system with more than one RDRAM, there will never be more than two RDRAMs with unretired write buffers. This is because INFINEON Technologies 34 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) a WR command issued to one device automatically retires the write buffers of all other devices written a time tRTR before or earlier. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RC ROW2... ROW0 ACT a0 PRER a2 ACT c0 The retire operation puts the write data in the new row t RAS COL4...COL0 WR a1 RD b1 RD b2 RD b3 t RP RD b4 RD b5 RD b6 retire (a1) MSK (a1) t RCD t RTR t CWD DQA8...0 DQB8...0 Transaction a: WR Transaction b: RD Transaction c: WR a0 = {Da, Ba, Ra} b1 = {Da, Bb, Cb1} b4 = {Da, Bb, Cb4} c0 = {Da, Ba, Rc} D (a1) t CAC Q (b1) Q (b2) Q (b3) Q (b4) Q (b5) a1 = {Da, Ba, Ca1} b2 = {Da, Bb, Cb2} b5 = {Da, Bb, Cb5} a2 = {Da, Ba} b3 = {Da, Bb, Cb3} b6 = {Da, Bb, Cb6} WARNING This sequence is hazardous and must be used with caution SPT04223 Figure 19 Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row INFINEON Technologies 35 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Interleaved Write - Example Figure 20 shows an example of an interleaved write transaction. Transactions similar to the one presented in Figure 16 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once every tRR interval rather than once every tRC interval (four times more often). The DQ data pin efficiency is 100% with this sequence. With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are precharged using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW pins. In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have completed by then (tRC has elapsed). Each transaction may use any value of row address (Ra, Rb, ...) and column address (Ca1, Ca2, Cb1, Cb2, ...). T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RC ROW2... ROW0 ACT a0 ACT b0 ACT c0 ACT d0 ACT e0 Transaction e can use the same bank as transaction a ACT f0 t RCD COL4...COL0 t RR WR a1 WR b1 WR b2 WR c1 WR c2 WR d1 WR d2 WR e1 WR e2 WR a2 WR z1 WRA z2 MSK (y1) MSK (y2) MSK (z1) MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2) MSK (c1) MSK (c2) MSK (d1) MSK (d2) t CWD DQA8...0 DQB8...0 D (x2) D (y1) D (y2) D (z1) D (z2) D (a1) D (a2) D (b1) D (b2) D (c1) D (c2) D (d1) Transaction y: WR Transaction z: WR Transaction a: WR Transaction b: WR Transaction c: WR Transaction d: WR Transaction e: WR Transaction f: WR y0 = {Da, Ba+4, Ry} z0 = {Da, Ba+6, Rz} a0 = {Da, Ba, Ra} b0 = {Da, Ba+2, Rb} c0 = {Da, Ba+4, Rc} d0 = {Da, Ba+6, Rd} e0 = {Da, Ba, Re} f0 = {Da, Ba+2, Rf} y1 = {Da, Ba+4, Cy1} z1 = {Da, Ba+6, Cz1} a1 = {Da, Ba, Ca1} b1 = {Da, Ba+2, Cb1} c1 = {Da, Ba+4, Cc1} d1 = {Da, Ba+6, Cd1} e1 = {Da, Ba, Ce1} f1 = {Da, Ba+2, Cf1} y2 = {Da, Ba+4, Cy2} z2 = {Da, Ba+6, Cz2} a2 = {Da, Ba, Ca2} b2 = {Da, Ba+2, Cb2} c2 = {Da, Ba+4, Cc2} d2 = {Da, Ba+6, Cd2} e2 = {Da, Ba, Ce2} f2 = {Da, Ba+2, Cf2} y3 = {Da, Ba+4} z3 = {Da, Ba+6} a3 = {Da, Ba} b3 = {Da, Ba+2} c3 = {Da, Ba+4} d3 = {Da, Ba+6} e3 = {Da, Ba} f3 = {Da, Ba+2} SPA04224 Figure 20 Interleaved Write Transaction with Two Dualoct Data Length INFINEON Technologies 36 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Interleaved Read - Example Figure 21 shows an example of interleaved read transactions. Transactions similar to the one presented in Figure 15 are directed to non-adjacent banks of a single RDRAM. The address sequence is identical to the one used in the previous write example. The DQ data pins efficiency is also 100%. The only difference with the write example (aside from the use of the RD command rather than the WR command) is the use of the PREX command in a COLX packet to precharge the banks rather than the RDA command. This is done because the PREX is available for a read transaction but is not available for a masked write transaction. Interleaved RRWW - Example Figure 22 shows a steady-state sequence of 2-dualoct RD/RD/WR/WR... transactions directed to non-adjacent banks of a single RDRAM. This is similar to the interleaved write and read examples in Figure 20 and Figure 21 except that bubble cycles need to be inserted by the controller at read/write boundaries. The DQ data pin efficiency for the example in Figure 22 is 32/42 or 76%. If there were more RDRAMs on the Channel, the DQ pin efficiency would approach 32/34 or 94% for the two-dualoct RRWW sequence (this case is not shown). In Figure 22, the first bubble type tCBUB1 is inserted by the controller between a RD and WR command on the COL pins. This bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in Figure 4. This bubble appears on the DQA and DQB pins as tDBUB1 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as tRBUB1. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RC ROW2... ROW0 ACT a0 ACT b0 ACT c0 ACT d0 ACT e0 Transaction e can use the same bank as transaction a ACT f0 t RCD COL4...COL0 RD z1 RD z2 PREX y3 RD a1 RD a2 PREX z3 RD b1 RD b2 PREX a3 RD c1 t RR RD c2 PREX b3 RD d1 RD d2 PREX c3 RD e1 RD e2 PREX t CAC DQA8...0 DQB8...0 Q (x2) Q (y1) Q (y2) Q (z1) Q (z2) Q (a1) Q (a2) Q (b1) Q (b2) Q (c1) Q (c2) Q (d1) Transaction y: RD Transaction z: RD Transaction a: RD Transaction b: RD Transaction c: RD Transaction d: RD Transaction e: RD Transaction f: RD y0 = {Da, Ba+4, Ry} z0 = {Da, Ba+6, Rz} a0 = {Da, Ba, Ra} b0 = {Da, Ba+2, Rb} c0 = {Da, Ba+4, Rc} d0 = {Da, Ba+6, Rd} e0 = {Da, Ba, Re} f0 = {Da, Ba+2, Rf} y1 = {Da, Ba+4, Cy1} z1 = {Da, Ba+6, Cz1} a1 = {Da, Ba, Ca1} b1 = {Da, Ba+2, Cb1} c1 = {Da, Ba+4, Cc1} d1 = {Da, Ba+6, Cd1} e1 = {Da, Ba, Ce1} f1 = {Da, Ba+2, Cf1} y2 = {Da, Ba+4, Cy2} z2 = {Da, Ba+6, Cz2} a2 = {Da, Ba, Ca2} b2 = {Da, Ba+2, Cb2} c2 = {Da, Ba+4, Cc2} d2 = {Da, Ba+6, Cd2} e2 = {Da, Ba, Ce2} f2 = {Da, Ba+2, Cf2} y3 = {Da, Ba+4} z3 = {Da, Ba+6} a3 = {Da, Ba} b3 = {Da, Ba+2} c3 = {Da, Ba+4} d3 = {Da, Ba+6} e3 = {Da, Ba} f3 = {Da, Ba+2} SPT04225 Figure 21 Interleaved Read Transaction with Two Dualoct Data Length 37 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) The second bubble type tCBUB2 is inserted (as a NOCOP command) by the controller between a WR and RD command on the COL pins when there is a WR-WR-RD sequence to the same device. This bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in Figure 18. There would be no bubble if address c0 and address d0 were directed to different devices. This bubble appears on the DQA and DQB pins as tDBUB2 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as tRBUB2. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RBUB2 ROW2... ROW0 ACT a0 ACT b0 ACT c0 t RBUB2 t CBUB1 Transaction e can use the same bank as transaction a ACT d0 ACT e0 t CBUB2 COL4...COL0 RD z1 RD z2 RD a1 RD a2 PREX z3 t CBUB2 RD d0 WR b1 WRA b2 WR c1 WRA c2 NOCOP NOCOP MSK (y2) PREX a3 MSK (b1) MSK (b2) MSK (c1) MSK (c2) t DBUB1 DQA8...0 DQB8...0 D (y2) t DBUB2 Q (z1) Q (z2) Q (a1) Q (a2) D (b1) D (b2) D (c1) t DBUB1 D (c2) Transaction y: WR Transaction z: RD Transaction a: RD Transaction b: WR Transaction c: WR Transaction d: RD Transaction e: RD Transaction f: WR y0 = {Da, Ba+4, Ry} z0 = {Da, Ba+6, Rz} a0 = {Da, Ba, Ra} b0 = {Da, Ba+2, Rb} c0 = {Da, Ba+4, Rc} d0 = {Da, Ba+6, Rd} e0 = {Da, Ba, Re} f0 = {Da, Ba+2, Rf} y1 = {Da, Ba+4, Cy1} z1 = {Da, Ba+6, Cz1} a1 = {Da, Ba, Ca1} b1 = {Da, Ba+2, Cb1} c1 = {Da, Ba+4, Cc1} d1 = {Da, Ba+6, Cd1} e1 = {Da, Ba, Ce1} f1 = {Da, Ba+2, Cf1} y2 = {Da, Ba+4, Cy2} z2 = {Da, Ba+6, Cz2} a2 = {Da, Ba, Ca2} b2 = {Da, Ba+2, Cb2} c2 = {Da, Ba+4, Cc2} d2 = {Da, Ba+6, Cd2} e2 = {Da, Ba, Ce2} f2 = {Da, Ba+2, Cf2} y3 = {Da, Ba+4} z3 = {Da, Ba+6} a3 = {Da, Ba} b3 = {Da, Ba+2} c3 = {Da, Ba+4} d3 = {Da, Ba+6} e3 = {Da, Ba} f3 = {Da, Ba+2} SPT04226 Figure 22 Interleaved RRWW Sequence with Two Dualoct Data Length INFINEON Technologies 38 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register Transactions The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the RDRAM. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the RDRAM. SCK (serial clock) and CMD (command) are driven by the controller to all RDRAMs in parallel. SIO0 and SIO1 are connected (in a daisy chain fashion) from one RDRAM to the next. In normal operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next RDRAM (the data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the first RDRAM. T4 T20 T36 T52 T68 1 SCK 0 Next transaction 1 CMD 1111 0000 00000000...00000000 00000000...00000000 00000000...00000000 00000000...00000000 1111 0 1 SIO0 SRQ-SWR Command Each packet is repeated from SIO0 to SIO1 SA SD SINT 0 1 SIO1 SRQ - SWR Command SA SD SINT 0 SPT04227 Figure 23 Serial Write (SWR) Transaction to Control Register Write and read transactions are each composed of four packets, as shown in Figure 23 and Figure 24. Each packet consists of 16 bits, as summarized in Figure 15 and Figure 16. The packet bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request) packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the SOP3...SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5...SDEV0 (Serial Device address) selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is set, then all RDRAMs are selected. The SA (Serial Address) packet contains a 12 bit address for selecting a control register. A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This provides delay for the selected RDRAM to access the control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet types. The SCK cycle time will accommodate the total delay. INFINEON Technologies 39 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T4 T20 T36 T52 T68 1 SCK 0 Next transaction 1 CMD 1111 0000 00000000...00000000 00000000...00000000 00000000...00000000 Addressed RDRAM drives 0/SD15...SD0/0 on SIO0 00000000...00000000 Controller drives 0 on SIO0 1111 0 1 SIO0 SRQ-SRD Command SA SINT 0 SD 0 0 First 3 packets are repeated from SIO0 to SIO1 Non-addressed RDRAMs pass 0/SD15...SD0/0 from SIO1 to SIO0 1 SINT 0 SIO1 SRQ - SRD Command SA SD 0 0 SPT04228 Figure 24 Serial Read (SRD) Transaction Control Register INFINEON Technologies 40 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register Packets T4 T20 1 SCK 0 1 CMD 1111 0000 00000000...00000000 0 1 SIO0 SRQ packet-SETR/CLRR/SETF 0 The packet is repeated from SIO0 to SIO1 1 SIO1 SRQ packet - SETR/CLRR/SETF 0 SPT04229 Figure 25 SETR, CLRR, SETF Transaction Table 15 summarizes the formats of the four packet types for control register transactions. Table 16 summarizes the fields that are used within the packets. Figure 25 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands. The same framing sequence on the CMD input is used, however. These commands are used during initialization prior to any control register read or write transactions. Table 15 Control Register Packet Formats SCK Cycle SIO0 or SIO0 or SIO1 SIO1 for SA for SRQ rsrv rsrv rsrv rsrv rsrv SDEV5 SOP3 SOP2 rsrv rsrv rsrv rsrv SA11 SA10 SA9 SA8 SIO0 or SIO0 or SCK SIO1 Cycle SIO1 for SD for SINT 0 0 0 0 0 0 0 0 SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 8 9 10 11 12 13 14 15 SIO0 or SIO0 or SIO1 SIO1 for SA for SRQ SOP1 SOP0 SBC SDEV4 SDEV3 SDEV2 SDEV1 SDEV0 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SIO0 or SIO0 or SIO1 SIO1 for SD for SINT 0 0 0 0 0 0 0 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 1 2 3 4 5 6 7 INFINEON Technologies 41 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 16 Field Description for Control Register Packets Field rsrv SOP3 ... SOP0 Description Reserved. Should be driven as "0" by controller. 0000 - SRD. Serial read of control register {SA11 ... SA0} of RDRAM {SDEV5 ... SDEV0}. 0001 - SWR. Serial write of control register {SA11 ... SA0} of RDRAM {SDEV5 ... SDEV0}. 0010 - SETR. Set Reset bit, all control registers assume their reset values.1) 16 tSCYCLE delay until CLRR command. 0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command. 1011 - CLRR. Clear Reset bit, all control registers retain their reset values.1) 4 tSCYCLE delay until next command. 1111 - NOP. No serial operation. 0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings. SDEV5 ... SDEV0 SBC SA11...SA0 SD15...SD0 1) Serial device. Compared to SDEVID5...SDEVID0 field of INIT control register field to select the RDRAM to which the transaction is directed. Serial broadcast. When set, RDRAMs ignore {SDEV5 ... SDEV0} for RDRAM selection. Serial address. Selects which control register of the selected RDRAM is read or written. Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called "SETR/CLRR Reset". INFINEON Technologies 42 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Initialization T0 T16 1 SCK 0 1 CMD 00001100 00000000...00000000 0 1 SIO0 0000000000000000 0 The packet is repeated from SIO0 to SIO1 1 SIO1 0000000000000000 0 SPT04230 Figure 26 SIO Reset Sequence Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by (primarily) using a sequence of control register transactions on the serial CMOS pins. The following steps outline the sequence seen by the various memory subsystem components (including the RDRAM components) during initialization. This sequence is available in the form of reference code. Contact Rambus Inc. for more information. 1. Start Clocks - This step calculates the proper clock frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG component), CTM (RDRAM component), and SCK (SIO block). 2. RAC Initialization - This step causes the INIT block to generate a sequence of pulses which resets the RAC, performs RAC maintenance operations, and measures timing intervals in order to ensure clock stability. 3. RDRAM Initialization - This stage performs most of the steps needed to initialize the RDRAMs. The rest are performed in stages 5.0, 6.0, and 7.0. All of the steps in 3.0 are carried out through the SIO block interface. 3.1./3.2. SIO Reset - This reset operation is performed before any SIO control register read or write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the INIT register into a special state (all bits cleared except SKP and SDEVID fields are set to ones). 3.3. Write TEST77 Register - The TEST77 register must be explicitly written with zeros before any other registers are read or written. 3.4. Write TCYCLE Register - The TCYCLE register is written with the cycle time tCYCLE of the CTM clock (for Channel and RDRAMs) in units of 64ps. The tCYCLE value is determined in stage 1.0. 3.5. Write SDEVID Register - The SDEVID (serial device identification) register of each RDRAM is written with a unique address value so that directed SIO read and write transactions can be performed. This address value increases from 0 to 31 according to the distance an RDRAM is from the ASIC component on the SIO bus (the closest RDRAM is address 0). INFINEON Technologies 43 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) 3.6. Write DEVID Register - The DEVID (device identification) register of each RDRAM is written with a unique address value so that directed memory read and write transactions can be performed. This address value increases from 0 to 31. The DEVID value is not necessarily the same as the SDEVID value. RDRAMs are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type). 3.7. Write PDNX,PDNXA Registers - The PDNX and PDNXA registers are written with values that are used to measure the timing intervals connected with an exit from the PDN (powerdown) power state. 3.8. Write NAPX Register - The NAPX register is written with values that are used to measure the timing intervals connected with an exit from the NAP power state. 3.9. Write TPARM Register - The TPARM register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set each RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0. 3.10. Write TCDLY1 Register - The TCDLY1 register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set each RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0. 3.11. Write TFRM Register - The TFRM register is written with a value that is related to the tRCD parameter for the system. The tRCD parameter is the time interval between a ROW packet with an activate command and the COL packet with a read or write command. 3.12. 3.12 SETR/CLRR - Each RDRAM is given a SETR command and a CLRR command through the SIO block. This sequence performs a second reset operation on the RDRAMs. 3.13. Write CCA and CCB Registers - These registers are written with a value halfway between their minimum and maximum values. This shortens the time needed for the RDRAMs to reach their steady-state current control values in stage 5.0. 3.14. Powerdown Exit - The RDRAMs are in the PDN power state at this point. A broadcast PDNExit command is performed by the SIO block to place the RDRAMs in the RLX (relax) power state in which they are ready to receive ROW packets. 3.15. SETF - Each RDRAM is given a SETF command through the SIO block. One of the operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM to a particular read domain. 4. Controller Configuration - This stage initializes the controller block. Each step of this stage will set a field of the ConfigRMC[63:0] bus to the appropriate value. Other controller implementations will have similar initialization requirements, and this stage may be used as a guide. 4.1. Initial Read Data Offset - The ConfigRMC bus is written with a value which determines the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The value written sets RMC.d1 to the minimum value permitted for the system. This will be adjusted later in stage 6.0. 4.2. Configure Row/Column Timing - This step determines the values of the tRAS,MIN, tRP,MIN, tRC,MIN, tRCD,MIN, tRR,MIN, and tPP,MIN RDRAM timing parameters that are present in the system. The ConfigRMC bus is written with values that will be compatible with all RDRAM devices that are present. 4.3. Set Refresh Interval - This step determines the values of the tREF,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. INFINEON Technologies 44 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) 4.4. Set Current Control Interval - This step determines the values of the tCCTRL,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 4.5. Set Slew Rate Control Interval - This step determines the values of the tTEMP,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 4.6. Set Bank/Row/Col Address Bits - This step determines the number of RDRAM bank, row, and column address bits that are present in the system. It also determines the RDRAM core types (independent, doubled, or split) that are present. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 5. RDRAM Current Control - This step causes the INIT block to generate a sequence of pulses which performs RDRAM maintenance operations. 6. RDRAM Core, Read Domain Initialization - This stage completes the RDRAM initialization 6.1. RDRAM Core Initialization - A sequence of 192 memory refresh transactions is performed in order to place the cores of all RDRAMs into the proper operating state. 6.2. RDRAM Read Domain Initialization - A memory write and memory read transaction is performed to each RDRAM to determine which read domain each RDRAM occupies. The programmed delay of each RDRAM is then adjusted so the total RDRAM read delay (propagation delay plus programmed delay) is constant. The TPARM and TCDLY1 registers of each RDRAM are rewritten with the appropriate read delay values. The ConfigRMC bus is also rewritten with an updated value. 7. Other RDRAM Register Fields - This stage rewrites the INIT register with the final values of the LSR, NSR, and PSR fields. In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it must read the SPD device present on each RIMM), it must process this information, and then it must write all the read-write registers to place the RDRAMs into the proper operating mode. Initialization Note [1]: During the initialization process, it is necessary for the controller to perform 128 current control operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown (PDN) exit. Initialization Note [2]: There are two classes of 64/72Mbit RDRAM. They are distinguished by the "S28IECO" bit in the SPD. The behavior of the RDRAM at initialization is slightly different for the two types: S28IECO = 0: Upon powerup the device enters ATTN state. The serial operations SETR, CLRR, and SETF are performed without requiring a SDEVID match of the SBC bit (broadcast) to be set. S28IECO = 1: Upon powerup the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization procedure for more information on how to handle this in a system. Initialization Note [3]: After the step of equalizing the total read delay of each RDRAM has been completed (i.e. after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read INFINEON Technologies 45 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) transaction should be made to each RDRAM in order to ensure that the output pipeline stages have been cleared. Initialization Note [4]: The SETF command (in the serial SRQ packet) should only be issued once during the Initialization process, as should the SETR and CLRR commands. Initialization Note [5]: The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an indeterminate state. Control Register Summary Table 17 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 27 through Figure 43. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM SPD Application Note (DL-0054) describes additional read-only configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram. Table 17 Control Register Summary SA11...SA0 02116 Register INIT Field SDEVID PSX SRP NSR PSR LSR TEN TSQ DIS 02216 02316 TEST34 CNFGA TEST34 REFBIT DBL MVER PVER read-write/ read-only read-write, 6 bits read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit Description Serial device ID. Device address for control register read/write. Power select exit. PDN/NAP exit with device addr on DQA5 ... 0. SIO repeater. Used to initialize RDRAM. NAP self-refresh. Enables self-refresh in NAP mode. PDN self-refresh. Enables self-refresh in PDN mode. Low power self-refresh. Enables low power self-refresh. Temperature sensing enable. Temperature sensing output. RDRAM disable. read-write, 16 bits Test register. Do not read or write after SIO reset. read-only, 3 bit read-only, 1 bit read-only, 6 bit read-only, 6 bit Refresh bank bits. Used for multi-bank refresh. Double. Specifies doubled-bank architecture Manufacturer version. Manufacturer identification number. Protocol version. Specifies version of Direct protocol supported. INFINEON Technologies 46 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 17 Control Register Summary (cont'd) SA11...SA0 02416 Register CNFGB Field BYT read-write/ read-only read-only, 1 bit Description Byte. Specifies an 8-bit or 9-bit byte size. Device type. Device can be RDRAM or some other device category. Split-core. Each core half is an individual dependent core. Core organization. Bank, row, column address field sizes. Stepping version. Mask version number. Device ID. Device address for memory read/write. Refresh bank. Next bank to be refreshed by self-refresh. Refresh row. Next row to be refreshed by REFA, selfrefresh. Current control A. Controls IOL output current for DQA. Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA. Current control B. Controls I OL output current for DQB. Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB. NAP exit. Specifies length of NAP exit phase A. NAP exit. Specifies length of NAP exit phase A + phase B. DQ select. Selects CMD framing for NAP/PDN exit. DEVTYP read-only, 3 bit SPT CORG SVER 04016 04116 04216 04316 DEVID REFB REFR CCA DEVID REFB REFR CCA ASYMA 04416 CCB CCB ASYMB 04516 NAPX NAPXA NAPX DQS 04616 04716 04816 PDNXA PDNX TPARM PDNXA PDNX TCAS TCLS TCDLY0 04916 04a16 04c16 TFRM TCDLY1 TCYCLE TFRM TCDLY1 read-only, 1 bit read-only, 6 bit read-only, 6 bit read-write, 5 bits read-write, 4 bits read-write, 9 bits read-write, 7 bits read-write, 2 bits read-write, 7 bits read-write, 2 bits read-write, 5 bits read-write, 5 bits read-write, 1 bits read-write, 13 bits PDN exit. Specifies length of PDN exit phase A. read-write, 13 bits PDN exit. Specifies length of PDN exit phase A + phase B. read-write, 2 bits read-write, 2 bits read-write, 3 bits read-write, 4 bits read-write, 3 bits tCAS-C core parameter. Determines tOFFP data sheet parameter. tCLS-C core parameter. Determines tCAC and tOFFP parameters. tCDLY0-C core parameter. Programmable delay for read data. tFRM-C core parameter. Determines ROW-COL packet framing interval. tCDLY1-C core parameter. Programmable delay for read data. TCYCLE read-write, 14 bits tCYCLE data sheet parameter. Specifies cycle time in 64 ps units. INFINEON Technologies 47 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 17 Control Register Summary (cont'd) SA11...SA0 04b16 Register SKIP Field AS MSE MS 04d1604e1604f1608016 - 0ff16 TEST77 TEST78 TEST79 reserved TEST77 TEST78 TEST79 read-write/ read-only read-only, 1 bit read-write, 1 bit read-write, 1 bit Description Autoskip value established by the SETF command. Manual skip enable. Allows the MS value to override the AS value. Manual skip value. read-write, 16 bits Test register. Write with zero after SIO reset. read-write, 16 bits Test register. Do not read or write after SIO reset. read-write, 16 bits Test register. Do not read or write after SIO reset. Vendor-specific test registers. Do not read or write after SIO reset. reserved vendor-specific INFINEON Technologies 48 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Read/write register. Reset values are undefined except as affected by SIO Reset as noted below. SETR/CLRR Reset does not affect this register. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDEVID5..0 - Serial Device Identification. Compared to SDE 0 VID DIS TSQ TEN LSR PSR NSR SRP PSX 0 SDEVID4...SDEVID0 SDEV5..0 serial address field of serial request packet for 5 register read/write transactions. This determines which RDRAM is selected for the register read or write operation. SDEVID resets to 3F16. PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the DQA5..0 pins. PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a directed exit, PDEV4..0 (on DQA4..0) is compared to DEVID4..0 to select a device. SRP - SIO Repeater. Controls value on SIO; SIO1 = SIO0 if SRP = 1, SIO1 = 1 if SRP = 0 SRP resets to 1. NAP Self-Refresh. NSR = 1 enables self-refresh in NAP mode. NSR can't be set while in NAP mode. NSR resets to 0. PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can't be set while in PDN mode. PSR resets to 0. Low Power Self-Refresh. LSR = 1 enables longer self-refresh interval. The self-refresh supply current is reduced. LSR resets to 0. Temperature Sensing Enable. TEN = 1 enables temperature sensing circuitry, permitting the TSQ bit to be read to determine if a thermal trip point has been exceeded. TEN resets to 0. Temperature Sensing Output. TSQ = 1 when a temperature trip point has been exceeded, TSQ = 0 when it has not. TSQ is available during a current control operation (see Figure 51). RDRAM Disable. DIS = 1 causes RDRAM to ignore NAP/PDN exit sequence, DIS = 0 permits normal operation. This mechanism disables an RDRAM. DIS resets to 0. SPD04273 Control Register: INIT Address: 02116 Figure 27 INIT Register INFINEON Technologies 49 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: CNFGA Address: 02316 Read-only register. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PVER5...0 = 000001 MVER5...0 = mmmmmm DBL REFBIT2...0 1 = 100 REFBIT2..0 - Refresh Bank Bits. Specifies the number of bank address bits used by REFA and REFP commands. Permits multi-bank refresh in future RDRAMs. DBL - Doubled-Bank. DBL = 1 means the device uses a doubled-bank architecture with adjacent-bank dependency. DBL = 0 means no dependency. MVER5..0 - Manufacturer Version. Specifies the manufacturer identification number. Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the range of the PDNX field (PDNX[2:0] in the PDNX register) may not be large enough to specify the location of the restricted interval in Figure 47. In this case, the effective tS4 parameter must increase and no row or column packets may overlap the restricted interval. See Figure 47 and Table 19. PVER5..0 - Protocol Version. Specifies the Direct Protocol version used by this device: 0 - Compliant with version 0.62. 1 - Compliant with version 0.7 through this version. 2 to 63 - Reserved. SPD04274 Figure 28 CNFGA Register Control Register: CNFGB Address: 02416 Read-only register. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVER5...0 = ssssss CORG4...0 = xxxxx SPT DEVTYP2...0 BYT 1 = 000 B BYT - Byte width. B = 1 means the device reads and writes 9-bit memory bytes. B = 0 means 8 bits. DEVTYP2..0 - Device type. DEVTYP = 000 means that this device is an RDRAM. SPT - Split-core. SPT = 1 means the core is split, SPT = 0 means it is not. CORG4..0 - Core organization. This field specifies the number of bank (3, 4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or 7 bits) address bits. The encoding of this field will be specified in a later version of this document. SVER5..0 - Stepping version. Specifies the mask version number of this device. SPD04255 Figure 29 CNFGB Register INFINEON Technologies 50 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: TEST34 Address: 02216 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 Read/write registers. Reset value of TEST34 is zero ( from SIO Reset). This register are used for testing purposes. It must not be read or written after SIO Reset. SPD04276 Figure 30 TEST Register Control Register: DEVID Address: 04016 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 DEVID4...DEVID0 Read/write register. Reset value is undefined. Device Identification register. DEVID4..DEVID0 is compared to DR4..DR0, DC4..DC0, and DX4..DX0 fields for all memory read or write transactions. This determines which RDRAM is selected for the memory read or write transaction. SPD04277 Figure 31 DEVID Register INFINEON Technologies 51 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: REFB Address: 04116 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 REFB4...REFB0 Read/write register. Reset value is zero (from SETR/CLRR). Refresh Bank register. REFB4..REFB0 is the bank that will be refreshed next during self-refresh. REFB4..0 is incremented after each self-refresh activate and precharge operation pair. SPD04256 Figure 32 REFB Register Control Register: CCA Address: 04316 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 ASYMA 0 CCA6...CCA0 Read/write register. Reset value is zero (SETR/CLRR or SIO Reset). CCA6...CCA0 - Current Control A. Controls the I OL output current for the DQA8..DQA0 pins. ASYMB0 control the asymmetry of the VOL / VOH voltage swing about the VREF reference voltage for the DQA8...0 pins. SPD04279 Figure 33 CCA Register INFINEON Technologies 52 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: REFR Address: 04216 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000 REFR8...REFR0 Read/write register. Reset value is zero (from SETR/CLRR). Refresh Row register. REFR8...REFR0 is the row that will be refreshed next by the REFA command or by self-refresh. REFR8...0 is incremented when BR4...0 = 1111 for the REFA command. REFR8...0 is incremented when REFB4...0 = 1111 for self-refresh. SPD04257 Figure 34 REFR Register Control Register: CCB Address: 04416 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 ASYMB 0 CCB6...CCB0 Read/write register. Reset value is zero (SETR/CLRR or SIO Reset). CCB6...CCB0 - Current Control B. Controls the IOL output current for the DQB8...DQB0 pins. ASYMB0 control the asymmetry of the VOL / VOH voltage swing about the VREF reference voltage for the DQB8...0 pins. SPD04281 Figure 35 CCB Register INFINEON Technologies 53 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: NAPX Address: 04516 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 DQS NAPX4..0 NAPXA4..0 Read/write register. Reset value is undefined Note - tSCYCLE is tCYCLE1 (SCK cycle time). NAPXA4...0 - Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must satisfy: NAPXA * tSCYCLE tNAPXA,MAX Do not set this field to zero. NAPX4...0 - Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting NAP mode. It must satisfy: NAPX * tSCYCLE NAPXA * tSCYCLE + tNAPXB,MAX Do not set this field to zero. DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5 cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device selection on DQ5...0. See Figure 48 - This field must be written SPD04282 with a "1" for this RDRAM. Figure 36 NAPX Register Control Register: PDNXA Address: 04616 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 PDNXA12...0 Read/write register. Reset value is undefined PDNXA4...0 - PDN Exit Phase A. This field specifies the number of (64 * SCK cycle) units during the first phase for exiting PDN mode. It must satisfy: PDNXA * 64 * tSCYCLE tPDNXA, MAX Do not set this field to zero. Note - only PDNXA5...0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time). SPD04283 Figure 37 PDNXA Register INFINEON Technologies 54 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: PDNX Address: 04716 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 PDNX12...0 Read/write register. Reset value is undefined PDNX4...0 - PDN Exit Phase A plus B. This field specifies the number of (256 * SCK cycle) units during the first plus second phases for exiting PDN mode. It should satisfy: PDNX * 256 * tSCYCLE PDNXA * 64 * tSCYCLE + tPDNXB, MAX If this equation can't be satisfied, then the maximum PDNX value should be written, and the tS4 / tH4 timing window will be modified (seeFigure 49). Do not set this field to zero. Note - only PDNX2...0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time). SPD04284 Figure 38 PDNX Register Control Register: TPARM Address: 04816 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 TCDLY0 TCLS TCAS Read/write register. Reset value is undefined. TCAS1..0 - Specifies the tCAS-C core parameter in tCYCLE units. This should be "10" (2 * tCYCLE ). TCLS1..0 - Specifies the tCLS-C core parameter in tCYCLE units. Should be "10" (2 * tCYCLE). TCDLY0 - Specifies the tCDLY0-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all devices to be equalized. This field may be written with the values "010" (2 * tCYCLE ) through "101" (5 * tCYCLE ). TCDLY0 010 011 011 011 100 101 The equations relating the core parameters to the datasheet parameters follow: tCAS-C = 2 * tCYCLE tCLS-C = 2 * tCYCLE tCPS-C = 1 * tCYCLE Not programmable tOFFP = tCPS-C + tCAS-C + tCLS-C - 1 * tCYCLE = 4 * tCYCLE tRCD = tRCD-C + 1 * tCYCLE - tCLS-C = tRCD-C - 1 * tCYCLE tCAC = 3 * tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C (see table below for programming ranges) tCDLY0-C 2 * tCYCLE 3 * tCYCLE 3 * tCYCLE 3 * tCYCLE 4 * tCYCLE 5 * tCYCLE TCDLY1 000 000 001 010 010 010 tCDLY1-C 0 * tCYCLE 0 * tCYCLE 1 * tCYCLE 2 * tCYCLE 2 * tCYCLE 2 * tCYCLE tCAS @ tCYCLE = 3.3 ns tCAS @ tCYCLE = 2,5 ns 7 * tCYCLE not allowed 8 * tCYCLE 8 * tCYCLE 9 * tCYCLE 9 * tCYCLE 10 * tCYCLE 10 * tCYCLE 11 * tCYCLE 11 * tCYCLE 12* tCYCLE 12* tCYCLE SPD04285 Figure 39 TPARM Register INFINEON Technologies 55 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: TFRM Address: 04916 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000000 TFRM3...0 Read/write register. Reset value is undefined. TFRM3...0 - Specifies the position of the framing point in tCYCLE units. This value must be greater or equal to the tFRM,MIN parameter. This is the minimum offset between a ROW packet (which places a device at ATTN) and the first COL packet (directed to that device) which must be framed. This field may be written with the values "0111" (7 * tCYCLE ) through "1010" (10 * tCYCLE ). TFRM is usually set to the value which matches the largest tRCD,MIN parameter (modulo 4 * tCYCLE) that is present in an RDRAM in the memory system. Thus, if an RDRAM with tRCD, MIN = 11 * tCYCLE were present, then TFRM would be programmed to 7 * tCYCLE . SPD04286 Figure 40 TFRM Register Control Register: TCDLY1 Address: 04A16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCDLY1 Read/write register. Reset value is undefined. TCDLY1 - Specifies the value of the tCDLY1-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all devices to be equalized. This field may be written with the values "000" (0 * tCYCLE ) through "010" (2 * tCYCLE ). Refer to Figure 39 for more details. SPD04287 Figure 41 TRDLY Register INFINEON Technologies 56 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: SKIP Address: 04B16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 AS MSE MS 0000000000 Read/write register (except AS field). Reset value is zero (SIO Reset). AS - Autoskip. Read-only value determined by autoskip circuit and stored when SETF serial command is received by RDRAM during initial-ization. In figure 58, AS = 1 corresponds to the early Q(a1) packet and AS = 0 to the Q(a1) packet one tCYCLE later for the four uncertain cases. MSE - Manual skip enable (0 = auto, 1 = manual). MS - Manual skip (MS must be 1 when MSE = 1).> During initialization, the RDRAMs at the furthest point in the fifth read domain may have selected the AS = 0 value, placing them at the closest point in a sixth read domain. Setting the MSE/MS fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read SPD04288 domain. Figure 42 SKIP Register Control Register: TEST77 Control Register: TEST78 Control Register: TEST79 Address: 04D16 Address: 04E16 Address: 04F16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 Read/write registers. Reset value of TEST78, 79 is zero ( SIO Reset). Do not read or write TEST78, 79 after SIO reset. TEST77 must be written with zero after SIO reset. These registers must only be used for testing purposes. SPD04289 Figure 43 TEST Registers INFINEON Technologies 57 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Control Register: TCYCLE Address: 04C16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 TCYCLE13...TCYCLE0 Read/write register. Reset value is undefined TCYCLE13...0 - Specifies the value of the tCYCLE datasheet parameter in 64 ps units. For the tCYCLE, MIN of 2.5 ns (2500 ps), this field should be written with the value "00027 16 " (39 * 64 ps). SPD04290 Figure 44 TCYCLE Register Power State Management Table 18 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with self-refresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because the TCLK/RCLK block must resynchronize itself to the external clock signal. NAP state is another low-power state in which either self-refresh or REFA-refresh are used to maintain the core. See "Refresh" on page 64 for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP entry. This imposes a limit (tNLIMIT) on how long an RDRAM may remain in NAP state before briefly returning to STBY or ATTN to update this synchronization state. Table 18 Power State Summary Power State PDN Description Powerdown state. Blocks Consuming Power Self-refresh Power State NAP Description Nap state. Similar to PDN except lower wake-up latency. Attention state. Ready for ROW and COL packets. Blocks Consuming Power Self-refresh or REFA-refresh TCLK/RCLK-Nap REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ demux receiver Core power STBY Standby state. Ready for ROW packets. REFA-refresh TCLK/RCLK ROW demux receiver REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ mux transmitter Core power ATTN ATTNR Attention read state. Ready for ROW and COL packets. Sending Q (read data) packets. ATTNW Attention write state. Ready for ROW and COL packets. Ready for D (write data) packets. INFINEON Technologies 58 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Figure 45 summarizes the transition conditions needed for moving between the various power states. Note that NAP and PDN have been divided into two substates (NAP-A/NAP-S and PDN-A/PDN-S) to account for the fact that a NAP or PDN exit may be made to either ATTN or STBY states. At initialization, the SETR/CLRR Reset sequence will put the RDRAM into PDN-S state. The PDN exit sequence involves an optional PDEV specification and bits on the CMD and SIOIN pins. Once the RDRAM is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a non-broadcast ROWA packet or non-broadcast ROWR packet with the ATTN command. The RDRAM returns to STBY from these three states when it receives a RLX command. Alternatively, it may enter NAP or PDN state from ATTN or STBY states with a NAPR or PDNR command in an ROWR packet. The PDN or NAP exit sequence involves an optional PDEV specification and bits on the CMD and SIO0 pins. The RDRAM returns to the ATTN or STBY state it was originally in when it first entered NAP or PDN. An RDRAM may only remain in NAP state for a time tNLIMIT. It must periodically return to ATTN or STBY. The NAPRC command causes a napdown operation if the RDRAM's NCBIT is set. The NCBIT is not directly visible. It is undefined on reset. It is set by a NAPR command to the RDRAM, and it is cleared by an ACT command to the RDRAM. It permits a controller to manage a set of RDRAMs in a mixture of power states. STBY state is the normal idle state of the RDRAM. In this state all banks and sense amps have usually been left precharged and ROWA and ROWR packets on the ROW pins are being monitored. When a non-broadcast ROWA packet or non-broadcast ROWR packet (with the ATTN command) packet addressed to the RDRAM is seen, the RDRAM enters ATTN state (see the right side of Figure 46). This requires a time tSA during which the RDRAM activates the specified row of the specified bank. A time TFRM x tCYCLE after the ROW packet, the RDRAM will be able to frame COL packets (TFRM is a control register field - see Figure 40). Once in ATTN state, the RDRAM will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands. INFINEON Technologies 59 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Automatic ATTNR Automatic Automatic Automatic ATTNW Automatic Automatic ATTN RLX t NLIMIT NAPR x RLXR NAP-A PDEV.CMD x SIO0 NAPR x RLXR PDEV.CMD x SIO0 PDNR x RLXR PDN-A PDEV.CMD x SIO0 PDNR x RLXR PDN PDN-S NAP NAP-S PDNR NAPR ATTN PDEV.CMD x SIO0 SETR/CLRR STBY Notation: SETR/CLRR - SETR/CLRR Reset Sequence in SRQ Packets - PDNR Command in ROWR Packet PDNR - NAPR Command in ROWR Packet NAPR - RLX Command in ROWR Packet RLXR - RLX Command in ROWR, COLC, COLX Packets RLX - SIO0 Input Value SIO0 PDEV.CMD - (PDEV = DEVID) x (CMD = 01) - ROWA Packet (Non-Broadcast) or ROWR Packet ATTN (Non-Broadcast) with ATTN Command SPD04231 Figure 45 Power State Transition Diagram Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY state with a RLX command. A RLX command may be given in an ROWR, COLC, or COLX packet (see the left side of Figure 46). It is usually given after all banks of the RDRAM have been precharged; if other banks are still activated, then the RLX command would probably not be given. If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM's power state doesn't change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY. INFINEON Technologies 60 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Figure 47 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW packet. A time tASN is required to enter NAP state (this specification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time tCD after the NAPR command. The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with NAPR, then the RDRAM will return to STBY state when NAP is exited. Figure 47 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a ROW packet. A time tASP is required to enter PDN state (this specification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time tCD after the PDNR command. The RDRAM may be in ATTN or STBY state when the PDNR command is issued. When PDN state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with PDNR, then the RDRAM will return to STBY state when PDN is exited. The current- and slew-rate-control levels are re-established. The RDRAM's write buffer must be retired with the appropriate COP command before NAP or PDN are entered. Also, all the RDRAM's banks must be precharged before NAP or PDN are entered. The exception to this is if NAP is entered with the NSR bit of the INIT register cleared (disabling self-refresh in NAP). The commands for relaxing, retiring, and precharging may be given to the RDRAM as late as the ROPa0, COPa0, and XOPa0 packets in Figure 47. No broadcast packets nor packets directed to the RDRAM entering Nap or PDN may overlay the quiet window. This window extends for a time tNPQ after the packet with the NAPR or PDNR command. Figure 48 shows the NAP and PDN exit sequences. These sequences are virtually identical; the minor differences will be highlighted in the following description. Before NAP or PDN exit, the CTM/CFM clock must be stable for a time tCE. Then, on a falling and rising edge of SCK, if there is a "01" on the CMD input, NAP or PDN state will be exited. Also, on the falling SCK edge the SIO0 input must be at a 0 for NAP exit and 1 for PDN exit. If the PSX bit of the INIT register is 0, then a device PDEV5 ... 0 is specified for NAP or PDN exit on the DQA5 ... 0 pins. This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the original falling edge, depending upon the value of the DQS bit of the NAPX register. If the PSX bit of the INIT register is 1, then the RDRAM ignores the PDEV5 ... 0 address packet and exits NAP or PDN when the wake-up sequence is presented on the CMD wire. The ROW and COL pins must be quiet at a time tS4/tH4 around the indicated falling SCK edge (timed with the PDNX or NAPX register fields). After that, ROW and COL packets may be directed to the RDRAM which is now in ATTN or STBY state. Figure 49 shows the constraints for entering and exiting NAP and PDN states. On the left side, an RDRAM exits NAP state at the end of cycle T3. This RDRAM may not re-enter NAP or PDN state for an interval of tNU0. The RDRAM enters NAP state at the end of cycle T13. This RDRAM may not re-exit NAP state for an interval of tNU1. The equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. NAPX is the value in the NAPX field in the NAPX register. INFINEON Technologies 61 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 CTM/CFM ROW2... ROW0 COL4... COL0 DQA8...0 DQB8...0 RLXR CTM/CFM ROW2... ROW0 COL4... COL0 ROP a0 ROP = non-broadcast ROWA or ROWR/ATTN a0 = {d0, b0, r0} a1 = {d1, b1, c1} RLXC RLXX COP a1 XOP a1 COP a0 XOP a0 No COL packets may be placed in the three indicated positions; i.e. at (TFRM - {1, 2, 3}) * t CYCLE A COL packet to device d0 (or any other device) is okay at (TFRM) * t CYCLE or later. A COL packet to another device (d1!= d0) is okay at (TFRM - 4) * t CYCLE or earlier. TFRM * t CYCLE t AS Power State ATTN STBY DQA8...0 DQB8...0 t SA Power State STBY ATTN SPT04232 Figure 46 STBY Entry (left) and STBY Exit (right) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CTM/CFM CTM/CFM a0 = {d0, b0, r0, c0} a1 = {d1, b1,r1, c1} t CD ROW2... ROW0 ROP a0 (NAPR) Restricted ROP a1 ROW2... ROW0 COL4... COL0 t CD ROP a0 (PDNR) Restricted ROP a1 t NPQ COL4... COL0 DQA8...0 DQB8...0 COP a0 Restricted XOP a0 COP a1 XOP a1 t NPQ COP a0 Restricted XOP a0 COP a1 XOP a1 No ROW or COL packets directed to device d0 may overlap the restricted interval. No broadcast ROW packets may overlap the quiet interval ROW or COL packets to a device other than d0 may owerlap the restricted interval ROW or COL packets directed to device d0 after the restricted interval will be ignored PDN SPT04233 DQA8...0 DQB8...0 t ASN Power State a) t ASP NAP ATTN / STBY a) Power State ATTN / STBY a) The (eventual) NAP / PDN exit will be to the same ATTN / STBY state the RDRAM was in prior to NAP / PDN entry Figure 47 NAP Entry (left) and PDN Entry (right) On the right side of Figure 48, an RDRAM exits PDN state at the end of cycle T3. This RDRAM may not re-enter PDN or NAP state for an interval of tPU0. The RDRAM enters PDN state at the end of cycle T13. This RDRAM may not re-exit PDN state for an interval of tPU1. The equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. PDNX is the value in the PDNX field in the PDNX register. INFINEON Technologies 62 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM No ROW packets may overlap the restricted interval ROW2... ROW0 If PSX = 1 in Init register, then NAP/PDN exit is broadcast (no PDEV field). ROP No COL packets may overlap the restricted interval if device PDEV is exiting the NAP-A or PDN-A states COP XOP Restricted ROP t S4 t H4 Restricted COP XOP COL4...COL0 t S3 t S3 t H3 DQA8...0 DQB8...0 PDEV5...0 b PDEV5...0 b t H3 Effective hold becomes t H4 = t H4 + (PDNXA * 64 * t SCYCLE + t PDNXB, MAX ) - (PDNX * 256 * t SCYCLE ) if (PDNX * 256 * t SCYCLE ) < (PDNXA * 64 * t SCYCLE + t PDNXB, MAX ). t S4 t H4 DQS = 1 b, c t CE DQS = 0 b SCK CMD SIO0 0 0/1 a The packet is repeated from SIO0 to SIO1 1 SIO1 0/1 a (NAPX * t SCYCLE ) / (256 * PDNX * t SCYCLE ) Power State a) b) NAP / PDN DQS = 0 b DQS = 1 b STBY / ATTN d Use 0 for NAP exit, 1 for PDN exit Device selection timing slot is selected by DQS field of NAPX register c) The DQS field must be written with "1" for this RDRAM d) Exit to STBY or ATTN depends upon whether RLXR was asserted at NAP or PDN entry time SPT04234 Figure 48 NAP and PDN Exit INFINEON Technologies 63 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM NAP entry CTM/CFM PDN entry ROW2... ROW0 SCK NAP exit NAPR ROW2... ROW0 SCK PDN exit 0 NAPR CMD 0 1 CMD 0 1 0 t NU0 no entry to NAP or PDN t NU1 no exit t PU0 no entry to NAP or PDN t PU1 no exit t NU0 = 5 * t CYCLE + (2 + NAPX) * t SCYCLE t NU1 = 8 * t CYCLE - (0.5 * t SCYCLE ) if NSR = 0 t NU1 = 23 * t CYCLE if NSR = 1 t PU0 = 5 * t SCYCLE + (2 + 256 * PDNX) * t SCYCLE t PU1 = 8 * t SCYCLE - (0.5 * t SCYCLE ) if PSR = 0 t PU1 = 23 * t SCYCLE if PSR = 1 SPT04235 Figure 49 Refresh NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right) RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure 50 shows an example of this. The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control register in the RDRAM. When the command is broadcast and ATTN is set, the power state of the RDRAMs (ATTN or STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When Ba is equal to its maximum value, the RDRAM automatically increments REFR for the next REFA command. On average, these REFA commands are sent once every tREF/2BBIT+RBIT (where BBIT are the number of bank address bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every tREF interval. The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see Table 12). In the example, an ACT command is sent after tRR to address b0, a different (non-adjacent) bank than the REFA command. A second ACT command can be sent after a time tRC to address c0, the same bank (or an adjacent bank) as the REFA command. Note that a broadcast REFP command is issued a time tRAS after the initial REFA command in order to precharge the refreshed bank in all RDRAMs. After a bank is given a REFA command, no other core operations (activate or precharge) should be issued to it until it receives a REFP. It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and INFINEON Technologies 64 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) would be {Broadcast,Ba+2,REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank incrementing pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14, 0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16, 18, 20, 22, 31}. Every time bank 31 is reached, the REFA command would automatically increment the REFR register. A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called self-refresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control register bit set, then self-refresh is automatically started for the RDRAM. Self-refresh uses an internal time base reference in the RDRAM. This causes an activate and precharge to be carried out once in every tREF/2BBIT+RBIT interval. The REFB and REFR control registers are used to keep track of the bank and row being refreshed. Before a controller places an RDRAM into self-refresh mode, it should perform REFA/REFP refreshes until the bank address is equal to the maximum value. This ensures that no rows are skipped. Likewise, when a controller returns an RDRAM to REFA/REFP refresh, it should start with the minimum bank address value (zero). T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T41 T42 T43 T44 T45 T46 T47 CTM/CFM t RC ROW2... ROW0 REFA a0 ACT b0 REFP a1 ACT c0 REFA d0 t RR t RAS COL4...COL0 t RP t REF /2 BBIT + RBIT DQA8...0 DQB8...0 Transaction a: REFA Transaction b: XX Transaction c: XX Transaction a: REFA a0 = {Broadcast, Ba, REFR} b0 = {Db, /={Ba, Ba+1, Ba-1}, Rb} c0 = {Dc, ==Ba, Rc} d0 = {Broadcast, Ba+1, REFR} a1 = {Broadcast, Ba} BBIT = #bank address bits BBIT = #row address bits REFB = REFB3...REFB0 REFR = REFR8...REFR0 SPT04236 Figure 50 REFA/REFP Refresh Transaction Example Current and Temperature Control Figure 51 shows an example of a transaction which performs current control calibration. It is necessary to perform this operation once to every RDRAM in every tCCTRL interval in order to keep the IOL output current in its proper range. INFINEON Technologies 65 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) This example uses four COLX packets with a CAL command. These cause the RDRAM to drive four calibration packets Q(a0) a time tCAC later. An offset of tRDTOCC must be placed between the Q(a0) packet and read data Q(a1)from the same device. These calibration packets are driven on the DQA4 ... 3 and DQB4 ... 3 wires. The TSQ bit of the INIT register is driven on the DQA5 wire during same interval as the calibration packets. The remaining DQA and DQB wires are not used during these calibration packets. The last COLX packet also contains a SAM command (concatenated with the CAL command). The RDRAM samples the last calibration packet and adjusts its IOL current value. Unlike REF commands, CAL and SAM commands cannot be broadcast. This is because the calibration packets from different devices would interfere. Therefore, a current control transaction must be sent every tCCTRL/N, where N is the number of RDRAMs on the Channel. The device field Da of the address a0 in the CAL/SAM command should be incremented after each transaction. Figure 23 shows an example of a temperature calibration sequence to the RDRAM. This sequence is broadcast once every tTEMP interval to all the RDRAMs on the Channel. The TCEN and TCAL are ROP commands, and cause the slew rate of the output drivers to adjust for temperature drift. During the quiet interval tTCQUIET the devices being calibrated can't be read, but they can be written. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T42 T43 T44 T45 T46 T47 CTM/CFM Read data from the same device from an earlier RD command must be at this packet position or earlier. Read data from a different device from an earlier RD command can be anywhere prior to the Q(a0) packet. Read data from a different device from a later RD command can be anywhere after to the Q(a0) packet. Read data from a different device from a later RD command must be at this packet position or later. ROW2... ROW0 t CCTRL COL4...COL0 CAL a0 CAL a0 CAL a0 CAL/SAM a0 CAL a2 t CAC t READTOCC DQA8...0 DQB8...0 Q (a1) Q (a0) t CCSAMTOREAD Q (a1) Transaction a0: CAL/SAM Transaction a1: RD Transaction a2: CAL/SAM a0 = {Da, Bx} a1 = {Da, Bx} a2 = {Da, Bx} DQA5 of the first calibrate packet has the inverted TSQ bit of INIT control register; i.e. logic 0 or high voltage means hot temperature. When used for monitoring, it should be enabled with the DQA3 bit (current control one value) in case there is no RDRAM present: HotTemp = DQA5 * DQA3 Note that DQB3 could be used instead of DQA3. SPT04237 Figure 51 Current Control CAL/SAM Transaction Example INFINEON Technologies 66 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T32 T33 T34 T35 T36 T37 T38 T41 T42 T43 T44 T45 T46 T47 CTM/CFM Any ROW packet may be plased in the gap between the ROW packets with the TCEN and TCAL commands. t TEMP ROW2... ROW0 TCEN TCAL TCEN t TCEN COL4...COL0 t TCQUIET t TCAL DQA8...0 DQB8...0 No read data from devices being calibrated SPT04238 Figure 52 Temperature Calibration (TCEN-TCAL) Transactions to RDRAM INFINEON Technologies 67 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 19 Electrical Conditions Parameter and Conditions Junction temperature under bias Supply voltage Supply voltage droop (DC) during NAP interval (tNLIMIT) Supply voltage ripple (AC) during NAP interval (tNLIMIT) Supply voltage for CMOS pins (2.5 V controllers) Supply voltage for CMOS pins (1.8 V controllers) Termination voltage Reference voltage RSL data input - low voltage RSL data input - high voltage RSL data input swing: VDIS = VDIH - VDIL RSL data asymmetry: ADI = [(VDIH - VREF) + (VDIL - VREF)]/VDIS RSL clock input - crossing point of true and complement signals RSL clock input - common mode Symbol min. Limit Values max. 100 2.0 2.0 C % % 2.50 + 0.13 V 2.50 - 0.13 Unit TJ VDD, VDDA VDD,N, VDDA,N - VDD,N, VDDA,N - 2.0 VCMOS 2.50 - 0.13 1.80 - 0.1 2.50 + 0.25 V 1.80 + 0.2 V VTERM VREF VDIL VDIH VDIS ADI VX VCM VCIS,CTM VCIS,CFM VIL,CMOS VIH,CMOS 1.80 - 0.1 1.40 - 0.2 1.80 + 0.1 1.40 + 0.2 V V V V V % V V V V V V VREF - 0.5 VREF + 0.2 0.4 0 1.3 1.4 0.35 0.125 - 0.3 VREF - 0.2 VREF + 0.5 1.0 - 20 1.8 1.7 0.70 0.70 VCM = (VCIH + VCIL)/2 RSL clock input swing: VCIS = VCIH - VCIL (CTM, CTMN pins). RSL clock input swing: VCIS = VCIH - VCIL (CFM, CFMN pins). CMOS input low voltage CMOS input high voltage VCMOS/ 2 - 0.25 VCMOS/ 2 + 0.25 VCMOS + 0.3 INFINEON Technologies 68 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 20 Timing Conditions Parameter CTM and CFM cycle times (-600) CTM and CFM cycle times (-711) CTM and CFM cycle times (-800) CTM and CFM input rise and fall times CTM and CFM high and low times CTM-CFM differential (MSE/MS = 0/0) CTM-CFM differential (MSE/MS = 1/1)1) Domain crossing window Symbol Limit Values min. max. 3.83 3.83 3.83 0.5 60% 1.0 1.0 0.1 0.65 2),d Unit ns ns ns ns Figure Figure 53 Figure 53 Figure 53 Figure 53 Figure 53 Figure 42 Figure 53 Figure 59 Figure 54 Figure 54 Figure 54 Figure 54 tCYCLE 3.33 2.80 2.50 0.2 40% 0.0 0.9 - 0.1 0.2 tCR, tCF tCH, tCL tTR tDCW tCYCLE tCYCLE tCYCLE ns ns ns ns DQA/DQB/ROW/COL input rise/fall times tDR, tDF DQA/DQB/ROW/COL-to-CFM set/hold @ tS, tH tCYCLE = 3.33 ns DQA/DQB/ROW/COL-to-CFM set/hold @ 0.275 - 0.2403),4) - - 0.200d tCYCLE = 2.81 ns DQA/DQB/ROW/COL-to-CFM set/hold @ tCYCLE = 2.50 ns SIO0, SIO1 input rise and fall times CMD, SCK input rise and fall times SCK cycle time - Serial control register transactions SCK cycle time - Power transitions SCK high and low times CMD setup time to SCK rising or falling edge5) CMD hold time to SCK rising or falling edgec SIO0 setup time to SCK falling edge SIO0 hold time to SCK falling edge PDEV setup time on DQA5 ... 0 to SCK rising edge. PDEV hold time on DQA5 ... 0 to SCK rising edge. ROW2 ... 0, COL4 ... 0 setup time for quiet window tDR1, tDF1 tDR2, tDF2 tCYCLE1 - - 1000 10 5.0 2.0 - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 48, Figure 57 tCH1, tCL1 tS1 tH1 tS2 tH2 tS3 tH3 tS4 4.25 1.25 1 40 40 0 5.5 -1 5 tCYCLE tCYCLE Figure 48 Figure 48 ROW2 ... 0, COL4 ... 0 hold time for quiet tH4 window6) INFINEON Technologies 69 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 20 Timing Conditions (cont'd) Parameter CMOS input low voltage over/undershoot voltage duration is less than or equal to 5 ns CMOS input high voltage over/undershoot voltage duration is less than or equal to 5 ns Symbol Limit Values min. max. - 0.7 Unit Figure - VIL,CMOS VCMOS/ V 2 - 0.4 VCMOS + 0.7 - - - - - - 10.0 32 V VIH,CMOS VCMOS/ 2 + 0.4 4 12 - Quiet on ROW/COL bits during NAP/PDN tNPQ entry Offset between read data and CC packets tREADTOCC (same device) Offset between CC packet and read data (same device) CTM/CFM stable before NAP/PDN exit CTM/CFM stable after NAP/PDN entry ROW packet to COL packet ATTN framing delay Maximum time in NAP mode Refresh interval Current control interval Temperature control interval TCE command to TCAL command TCAL command to quiet window Quiet window (no read data) RDRAM delay (no RSL operations allowed) 1) tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE s ms CLE Figure 47 Figure 51 Figure 51 Figure 48 Figure 47 Figure 46 Figure 45 Figure 50 Figure 51 Figure 23 Figure 23 Figure 23 Figure 23 page 43 tCCSAMTOREAD 8 tCE tCD tFRM tNLIMIT tREF tCCTRL tTEMP tTCEN tTCAL tTCQUIET tPAUSE 2 100 7 - - 34 tCYCLE 100 ms ms/tCY - 150 2 140 - 100 - 2 - 200.0 ms tCYCLE tCYCLE tCYCLE s 2) 3) 4) 5) 6) MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0. This parameter also applies to a -800 or -711 part when operated with tCYCLE = 3.33 ns. This parameter also applies to a -800 part when operated with tCYCLE = 2.81 ns. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values. With VIL,CMOS = 0.5 VCMOS - 0.6 V and VIH,CMOS = 0.5 VCMOS + 0.6 V Effective hold becomes tH4 ' = tH4 + [PDNXA x 64 x tSCYCLE + tPDNXB,MAX] - [PDNX x 256 x tSCYCLE] if [PDNX x 256 x tSCYCLE] < [PDNXA x 64 x tSCYCLE + tPDNXB,MAX]. See Figure 48. INFINEON Technologies 70 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 21 Electrical Characteristics Parameter Symbol min. Limit Values max. 10 10 90.0 2.0 - 10.0 0.3 - A A mA mA A V V - 10 - 10 30.0 - 150 - 10.0 - Unit VREF current @ VREF,MAX RSL output high current @ (0 VOUT VDD) RSL IOL current @ VOL = 0.9 V, VDD,MIN, TJ,MAX1) RSL IOL current resolution step Dynamic output impedance CMOS input leakage current @ (0 VI,CMOS VCMOS) CMOS output voltage @ IOL,CMOS = 1.0 mA CMOS output high voltage @ IOH,CMOS = - 0.25 mA 1) IREF IOH IALL IOL rOUT II,CMOS VOL,CMOS VOH,CMOS VCMOS - 0.3 This measurement is made in manual current control mode; i.e. with all output device legs sinking current. Table 22 Timing Characteristics Parameter Symbol min. Limit Values max. 1),3) Unit Figure Figure 55 Figure 55 Figure 55 tQ CTM-to-DQA/DQB output time @ tCYCLE = 3.33 ns CTM-to-DQA/DQB output time @ tCYCLE = 2.81 ns CTM-to-DQA/DQB output time @ tCYCLE = 2.50 ns DQA/DQB output rise and fall times SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20 pF (SD read data valid). SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20 pF (SD read data hold). SIOOUT rise/fall @ CLOAD,MAX = 20 pF + 0.3501),3) ns - 0.350 2),3) - 0.300 + 0.3002),3) ns ns - 0.2603) + 0.2603) tQR, tQF tQ1 0.2 - 0.45 10 ns ns Figure 55 Figure 58 tHR 2 - ns Figure 58 tQR1, tQF1 tPROP1 tNAPXA tNAPXB tPDNXA tPDNXB - 5 10 50 40 4 9000 ns ns ns ns s Figure 58 Figure 58 Figure 48 Figure 48 Figure 48 SIO0-to-SIO1 or SIO1-to-SIO0 delay @ - CLOAD,MAX = 20 pF NAP exit delay - phase A NAP exit delay - phase B PDN exit delay - phase A PDN exit delay - phase B - - - - tCYCLE Figure 48 2.00 INFINEON Technologies 71 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 22 Timing Characteristics (cont'd) Parameter Symbol min. Limit Values max. 1 0 8 8 - - - - Unit Figure tAS tSA tASN tASP 1) 2) 3) ATTN-to-STBY power state delay STBY-to-ATTN power state delay ATTN/STBY-to-NAP power state delay ATTN/STBY-to-PDN power state delay tCYCLE Figure 46 tCYCLE Figure 46 tCYCLE Figure 47 tCYCLE Figure 47 This parameter also applies to a -800 or -711 part when operated with tCYCLE = 3.33 ns. This parameter also applies to a -800 part when operated with tCYCLE = 2.81 ns. tQ,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values. RSL - Clocking Figure 53 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CTM edge to the falling CTM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CTM. The tCR and tCF rise- and fall-time parameters are measured at the 20% and 80% points. INFINEON Technologies 72 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) t CYCLE t CL VCIH 80% CTM t CH t CR t CR VX50% 20% VCM VX+ VCIL CTMN t TR t CF t CR t CF t CR VCIH 80% CFM VX50% 20% VCM VX+ VCIL CFMN t CF t CL t CYCLE t CH t CF SPT04239 Figure 53 RSL Timing - Clock Signals The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CFM edge to the falling CFM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CFM. The tCR and tCF rise- and fall-time parameters are measured at the 20% and 80% points. The tTR parameter specifies the phase difference that may be tolerated with respect to the CTM and CFM differential clock inputs (the CTM pair is always earlier). INFINEON Technologies 73 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) RSL - Receive Timing Figure 54 is a timing diagram which shows the detailed requirements for the RSL input signals on the Channel. The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the Channel. Each signal is sampled twice per tCYCLE interval. The set/hold window of the sample points is tS/tH. The sample points are centered at the 0% and 50% points of a cycle, measured relative to the crossing points of the falling CFM clock edge. The set and hold parameters are measured at the VREF voltage point of the input transition. The tDR and tDF rise- and fall-time parameters are measured at the 20% and 80% points of the input transition. VCIH 80% CFM VX50% 20% VCM VX+ VCIL CFMN DQA 0.5 x t CYCLE tH t DR tS tS tH VDIH 80% DQB ROW COL Even Odd VREF 20% VDIL t DF Figure 54 RSL Timing - Data Signals for Receive SPT04240 INFINEON Technologies 74 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) RSL - Transmit Timing Figure 55 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel. The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel. Each signal is driven twice per tCYCLE interval. The beginning and end of the even transmit window is at the 75% point of the previous cycle and at the 25% point of the current cycle. The beginning and end of the odd transmit window is at the 25% point and at the 75% point of the current cycle. These transmit points are measured relative to the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal tCYCLE/2, as indicated by the non-zero values of tQ,MIN and tQ,MAX. The tQ parameters are measured at the 50% voltage point of the output transition. The tQR and tQF rise- and fall-time parameters are measured at the 20% and 80% points of the output transition. CTM VCIH 80% VX50% 20% VCM VX+ VCIL CTMN 0.75 x t CYCLE 0.25 x t CYCLE 0.75 x t CYCLE t Q, MAX DQA VQH 80% DQB t QR t Q, MAX t Q, MIN t Q, MIN Even 50% 20% Odd VQL t QF Figure 55 RSL Timing - Data Signals for Transmit SPT04241 CMOS - Receive Timing Figure 56 is a timing diagram which shows the detailed requirements for the CMOS input signals. The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM's SIO1 output. SCK is the CMOS clock signal driven by the controller. All signals are high true. INFINEON Technologies 75 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) The cycle time, high phase time, and low phase time of the SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the 50% level. The rise and fall times of SCK, CMD, and SIO0 are tDR1 and tDF1, measured at the 20% and 80% levels. The CMD signal is sampled twice per tCYCLE1 interval, on the rising edge (odd data) and the falling edge (even data). The set/hold window of the sample points is tS1/tH1. The SCK and CMD timing points are measured at the 50% level. The SIO0 signal is sampled once per tCYCLE1 interval on the falling edge. The set/hold window of the sample points is tS2/tH2. The SCK and SIO0 timing points are measured at the 50% level. VIH, CMOS SCK 80% 50% 20% t DR2 VIL, CMOS t DF2 t CH1 t DR2 t CYCLE1 t CL1 t H1 t H1 t S1 t S1 VIH, CMOS CMD 80% Even 50% 20% Odd VIL, CMOS t DF2 t DR1 VIH, CMOS 80% 50% 20% SIO0 t H2 t S2 VIL, CMOS t DF1 SPT04242 Figure 56 CMOS Timing - Data Signals for Receive 76 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) The SCK clock is also used for sampling data on RSL inputs in one situation. Figure 48 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (see Figure 27), then the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window tS3/tH3 around the rising edge of SCK. This is shown in Figure 57. The SCK timing point is measured at the 50% level, and the DQA[5:0] bus signals are measured at the VREF level. VIH, CMOS SCK 80% 50% 20% VIL, CMOS t H3 VDIH 80% PDEV DQA(5:0) t S3 VREF 20% VDIL SPT04243 Figure 57 CMOS Timing - Device Address for NAP or PDN Exit CMOS - Transmit Timing Figure 58 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per tCYCLE1 interval on the falling edge. The clock-to-output window is tQ1,MIN/tQ1,MAX. The SCK and SIO0 timing points are measured at the 50% level. The rise and fall times of SIO0 are tQR1 and tQF1, measured at the 20% and 80% levels. INFINEON Technologies 77 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) VIH, CMOS 80% 50% 20% SCK VIL, CMOS t Q1, MAX VOH, CMOS SIO0 80% 50% 20% t HR, MIN t QR1 VOL, CMOS SIO0 or SIO1 t QF1 t DR1 VIH, CMOS 80% 50% 20% VIL, CMOS t DF1 SIO1 or SIO0 t PROP1, MAX t PROP1, MIN t QR1 VOH, CMOS 80% 50% 20% VOL, CMOS t QF1 Figure 58 CMOS Timing - Data Signals for Transmit SPT04244 INFINEON Technologies 78 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Figure 58 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The tPROP1 parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1 inputs must be tDR1 and tDF1, measured at the 20% and 80% levels. The rise and fall times of SIO0 and SIO1 outputs are tQR1 and tQF1, measured at the 20% and 80% levels. RSL - Domain Crossing Window When read data is returned by the RDRAM, information must cross from the receive clock domain (CFM) to the transmit clock domain (CTM). The tTR parameter permits the CFM to CTM phase to vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. A second parameter tDCW is needed in order to describe how the delay between a RD command packet and read data packet varies as a function of the tTR value. Figure 59 shows this timing for five distinct values of tTR. Case A (tTR = 0) is what has been used throughout this document. The delay between the RD command and read data is tCAC. As tTR varies from zero to tCYCLE (cases A through E), the command to data delay is (tCAC - tTR). When the tTR value is in the range 0 to tDCW,MAX, the command to data delay can also be (tCAC - tTR - tCYCLE). This is shown as cases A' and B' (the gray packets). Similarly, when the tTR value is in the range (tCYCLE + tDCW,MIN) to tCYCLE, the command to data delay can also be (tCAC - tTR + tCYCLE). This is shown as cases D' and E' (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The delay value is selected at initialization, and remains fixed thereafter. INFINEON Technologies 79 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) CFM COL CTM DQA/B DQA/B CTM DQA/B DQA/B CTM DQA/B CTM Case D DQA/B DQA/B CTM Case E DQA/B DQA/B t CYCLE RD a1 t TR Case A t TR = 0 t CAC - t TR t CAC - t TR - t CYCLE Q(a1) Q(a1) Case A' t TR = 0 t TR Case B t TR = t DCW, max t CAC - t TR t CAC - t TR - t CYCLE Q(a1) Q(a1) Case B' t TR = t DCW, max t TR Case C t TR = 0.5 * t CYCLE t CAC - t TR Q(a1) t TR = t CYCLE + t DCW, min t CAC - t TR t CAC - t TR + t CYCLE t TR Q(a1) Q(a1) Case D' t TR = t CYCLE + t DCW, min t TR = t CYCLE t CAC - t TR t CAC - t TR + t CYCLE t TR Q(a1) Q(a1) SPA04245 Case E' t TR = t CYCLE Figure 59 RSL Transmit - Crossing Read Domains INFINEON Technologies 80 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Timing Parameters Table 23 Timing Parameter Summary Parameter Description Min -40 -800 Min -45 -800 28 Min -45 -711 28 Min -53 -600 28 Max Unit Figure tRC Row Cycle time of RDRAM banks - the 28 interval between ROWA packets with ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRER 1) command to the same bank. 20 - tCYCLE Figure 15 Figure 16 tRAS 20 20 20 64 s2) tCYCLE Figure 15 Figure 16 tRP Row Precharge time of RDRAM banks 8 the interval between ROWR packet with PRER a command and next ROWA packet with ACT command to the same bank. Precharge-to-precharge time of RDRAM 8 device - the interval between successive ROWR packets with PRERa commands to any banks of the same device. RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. 8 8 8 8 - tCYCLE Figure 15 Figure 16 tPP 8 8 8 - tCYCLE Figure 12 tRR 8 8 8 - tCYCLE Figure 13 tRCD RAS-to-CAS Delay - the interval from 7 ROWA packet with ACT command to COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen by the RDRAM core (tRCD-C ) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. CAS Access delay - the interval from RD 8 command to Q read data. The equation for tCAC is given in the TPARM register in Figure 39. CAS Write Delay (interval from WR command to D write data. CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands). Length of ROWA, ROWR, COLC, COLM or COLX packet. Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. 6 4 9 7 7 - tCYCLE Figure 15 Figure 16 tCAC 8 8 8 12 tCYCLE Figure 4 Figure 39 tCWD tCC 6 4 6 4 6 4 6 - tCYCLE Figure 4 tCYCLE Figure 15 Figure 16 tPACKET tRTR 4 8 4 8 4 8 4 8 4 - tCYCLE Figure 3 tCYCLE Figure 17 tOFFP The interval (offset) from COLC packet 4 with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register in Figure 39. 4 4 4 4 tCYCLE Figure 14 Figure 39 INFINEON Technologies 81 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 23 Timing Parameter Summary (cont'd) Parameter Description Min -40 -800 4 4 Min -45 -800 4 4 Min -45 -711 4 4 Min -53 -600 4 4 Max Unit Figure tRDP tRTP Interval from last COLC packet with RD command to ROWR packet with PRER. Interval from last COLC packet with automatic retire command to ROWR packet with PRER. - - tCYCLE Figure 15 tCYCLE Figure 16 1) 2) Or equivalent PREC or PREX command. See Figure 14. This is a constraint imposed by the core, and is therefore in units of s rather than tCYCLE . Table 24 Absolute Maximum Ratings Parameter Voltage applied to any RSL or CMOS pin with respect to GND Voltage on VDD and VDDA with respect to GND Storage temperature Symbol min. Limit Values max. - 0.3 - 0.5 - 50 Unit V V C VI,ABS VDD,ABS, VDDA,ABS TSTORE VDD + 0.3 VDD + 1.0 100 INFINEON Technologies 82 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) IDD - Supply Current Profile Table 25 Supply Current Profile RDRAM Blocks Consuming Power 1) IDD Value max. -800 Limit Values max. -711 3000 4 95 145 max. -600 3000 4 90 140 Unit Self-refresh only for INIT.LSR = 0 T/RCLK-Nap T/RCLK, ROW-demux T/RCLK, ROW-demux, COL-demux T/RCLK, ROW-demux, COL-demux, DQdemux, 1 x WR-SenseAmp, 4 x ACT-Bank T/RCLK, ROW-demux, COL-demux, DQmux, 1 x RD-SenseAmp, 4 x ACT-Bank 3) 1) 2) 3) IDD,PDN IDD,NAP IDD,STBY IDD,ATTN IDD,ATTN-W 3000 4 100 150 A mA mA mA 575/6352) 515/570 450/4952) mA IDD,ATTN-R 520/5752) 470/520 410/450 mA The CMOS interface consumes power in all power states. x16/x18 RDRAM data width. This does not include the IOL sink current. The RDRAM dissipates IOL x VOL in each output driver when a logic one is driven. INFINEON Technologies 83 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Capacitance and Inductance Figure 60 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device presents to the Channel. Pad L C R DQA, DQB, RQ Pin Gnd Pin Pad L C R CTM, CTMN, CFM, CFMN Pin Gnd Pin Pad L , CMOS SCK, CMD Pin C , CMOS Gnd Pin Pad L , CMOS SIO0, SIO1 Pin C , CMOS, SIO Gnd Pin SPT04246 Figure 60 Equivalent Load Circuit for RSL Pins 84 2.00 INFINEON Technologies Direct RDRAM 128/144-MBit (256Kx16/18x32s) This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling effects make the effective single-pin inductance LI, and capacitance CI, a function of neighboring pins, these parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel, the effective LI and CI are defined as the worst-case values over all specified operating conditions. LI is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment places each RSL signal adjacent to an AC ground (a GND or VDD pin), the effective inductance must be defined based on this configuration. Therefore, LI assumes a loop with the RSL pin adjacent to an AC ground. CI is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective package pin capacitance and the IO pad capacitance. Table 26 RSL Pin Parasitics Parameter and Conditions - RSL Pins RSL effective input inductance Mutual inductance between any DQA or DQB RSL signals. Mutual inductance between any ROW or COL RSL signals. Difference in LI value between any RSL pins of a single device. RSL effective input capacitance1) -800 RSL effective input capacitance1)-711 RSL effective input capacitance1)-600 Mutual capacitance between any RSL signals. LI Symbol min. Limit Values max. 4.0 0.2 0.6 1.8 2.4 2.4 2.6 0.1 0.06 15 nH nH nH nH pF pF pF pF pF - - - - 2.0 2.0 2.0 - - 4 Unit LI L12 CI C12 CI Difference in CI value between average of CTM/CFM and any RSL pins of a single device. RSL effective input resistance 1) RI This value is a combination of the device IO circuitry and package capacitances. Table 27 CMOS Pin Parasitics Parameter and Conditions - CMOS Pins CMOS effective input inductance CMOS effective input capacitance (SCK,CMD) 1) Symbol Limit Values min. max. 8.0 2.1 7.0 - 1.7 - Unit nH pF pF LI ,CMOS CI ,CMOS CI ,CMOS,SIO CMOS effective input capacitance (SIO1, SIO0)1) 1) This value is a combination of the device IO circuitry and package capacitances. INFINEON Technologies 85 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Center-Bonded FBGA Package Figure 61 shows the form and dimensions of the recommended package for the center-bonded CSP device class. D ABCDE 1 2 3 4 5 6 7 8 9 10 1 1 2 E1 d e1 E e2 A FGHJ Bottom T op Bottom Bottom Figure 61 Center-Bonded FBGA Package Table 28 lists the numerical values corresponding to dimensions shown in Figure 61. INFINEON Technologies 86 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Table 28 Center-Bonded FBGA Package Dimensions Parameter Ball pitch (x-axis) Ball pitch (y-axis) Package body length Package body width Package total thickness Ball height Ball diameter Symbol min. e1 e2 A D E E1 d 1.00 0.8 10.9 10.4 0.65 0.18 0.3 Limit Values max. 1.00 0.8 11.1 10.6 1.05 0.35 0.4 mm mm mm mm mm mm mm Unit INFINEON Technologies 87 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) Glossary of Terms ACT activate adjacent ASYM ATTN ATTNR ATTNW AV bank BC BBIT broadcast BR bubble BYT BX C CAL CBIT CCA CCB CFM,CFMN Channel CLRR CMD CNFGA CNFGB COL COL COLC COLM column command COLX Activate command from AV field. To access a row and place in sense amp. Two RDRAM banks which share sense amps (also called doubled banks). CCA register field for RSL VOL/VOH. Power state - ready for ROW/COL packets. Power state - transmitting Q packets. Power state - receiving D packets. Opcode field in ROW packets. A block of 2RBIT x 2CBIT storage cells in the core of the RDRAM. Bank address field in COLC packet. CNFGA register field - # bank address bits. An operation executed by all RDRAMs. Bank address field in ROW packets. Idle cycle(s) on RDRAM pins needed because of a resource constraint. CNFGB register field - 8/9 bits per byte. Bank address field in COLX packet. Column address field in COLC packet. Calibrate (IOL) command in XOP field. CNFGB register field - # column address bits. Control register - current control A. Control register - current control B. Clock pins for receiving packets. ROW/COL/DQ pins and external wires. Clear reset command from SOP field. CMOS pin for initialization/power control. Control register with configuration fields. Control register with configuration fields. Pins for column-access control. COLC,COLM,COLX packet on COL pins. Column operation packet on COL pins. Write mask packet on COL pins. Rows in a bank or activated row in sense amps have 2CBIT dualocts column storage. A decoded bit-combination from a field. Extended operation packet on COL pins. INFINEON Technologies 88 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) controller COP core CTM,CTMN D DBL DC device DEVID DM doubled-bank DQ DQA DQB DQS dualoct DX field INIT initialization LSR M MA MB MSK MVER NAP NAPR NAPRC NAPXA NAPXB NOCOP A logic-device which drives the ROW/COL /DQ wires for a Channel of RDRAMs. Column opcode field in COLC packet. The banks and sense amps of an RDRAM. Clock pins for transmitting packets. Write data packet on DQ pins. CNFGB register field - doubled-bank. Device address field in COLC packet. An RDRAM on a Channel. Control register with device address that is matched against DR, DC, and DX fields. Device match for ROW packet decode. RDRAM with shared sense amp. DQA and DQB pins. Pins for data byte A. Pins for data byte B. NAPX register field - PDN/NAP exit. 16 bytes - the smallest addressable datum. Device address field in COLX packet. A collection of bits in a packet. Control register with initialization fields. Configuring a Channel of RDRAMs so they are ready to respond to transactions. CNFGA register field - low-power self-refresh. Mask opcode field (COLM/COLX packet). Field in COLM packet for masking byte A. Field in COLM packet for masking byte B. Mask command in M field. Control register - manufacturer ID. Power state - needs SCK/CMD wakeup. Nap command in ROP field. Conditional nap command in ROP field. NAPX register field - NAP exit delay A. NAPX register field - NAP exit delay B. No-operation command in COP field. current control Periodic operations to update the proper IOL value of RSL output drivers. DR,DR4T,DR4F Device address field and packet framing fields in ROWA and ROWR packets. INFINEON Technologies 89 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) NOROP NOXOP NSR packet PDN PDNR PDNXA PDNXB pin efficiency PRE PREC precharge PRER PREX PSX PSR PVER Q R RBIT RD/RDA read receive REFA REFB REFBIT REFP REFR refresh retire RLX RLXC RLXR RLXX ROP No-operation command in ROP field. No-operation command in XOP field. INIT register field- NAP self-refresh. A collection of bits carried on the Channel. Power state - needs SCK/CMD wakeup. Powerdown command in ROP field. Control register - PDN exit delay A. Control register - PDN exit delay B. The fraction of non-idle cycles on a pin. PREC,PRER,PREX precharge commands. Precharge command in COP field. Prepares sense amp and bank for activate. Precharge command in ROP field. Precharge command in XOP field. INIT register field - PDN/NAP exit. INIT register field - PDN self-refresh. CNFGB register field - protocol version. Read data packet on DQ pins. Row address field of ROWA packet. CNFGB register field - # row address bits. Read (/precharge) command in COP field. Operation of accessing sense amp data. Moving information from the Channel into the RDRAM (a serial stream is demuxed). Refresh-activate command in ROP field. Control register - next bank (self-refresh). CNFGA register field - ignore bank bits (for REFA and self-refresh). Refresh-precharge command in ROP field. Control register - next row for REFA. Periodic operations to restore storage cells. The automatic operation that stores write buffer into sense amp after WR command. RLXC,RLXR,RLXX relax commands. Relax command in COP field. Relax command in ROP field. Relax command in XOP field. Row-opcode field in ROWR packet. INFINEON Technologies 90 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) row ROW ROW ROWA ROWR RQ RSL SAM SA SBC SCK SD SDEV SDEVID self-refresh sense amp SETF SETR SINT SIO0,SIO1 SOP SRD SRP SRQ STBY SVER SWR TCAS TCLS TCLSCAS TCYCLE TDAC TEST77 TEST78 TRDLY transaction 2CBIT dualocts of cells (bank/sense amp). Pins for row-access control ROWA or ROWR packets on ROW pins. Activate packet on ROW pins. Row operation packet on ROW pins. Alternate name for ROW/COL pins. Rambus Signaling Levels. Sample (IOL) command in XOP field. Serial address packet for control register transactions w/ SA address field. Serial broadcast field in SRQ. CMOS clock pin. Serial data packet for control register transactions w/ SD data field. Serial device address in SRQ packet. INIT register field - Serial device ID. Refresh mode for PDN and NAP. Fast storage that holds copy of bank's row. Set fast clock command from SOP field. Set reset command from SOP field. Serial interval packet for control register read/write transactions. CMOS serial pins for control registers. Serial opcode field in SRQ. Serial read opcode command from SOP. INIT register field - Serial repeat bit. Serial request packet for control register read/write transactions. Power state - ready for ROW packets. Control register - stepping version. Serial write opcode command from SOP. TCLSCAS register field - tCAS core delay. TCLSCAS register field - tCLS core delay. Control register - tCAS and tCLS delays. Control register - tCYCLE delay. Control register - tDAC delay. Control register - for test purposes. Control register - for test purposes. Control register - tRDLY delay. ROW,COL,DQ packets for memory access. INFINEON Technologies 91 2.00 Direct RDRAM 128/144-MBit (256Kx16/18x32s) transmit WR/WRA write XOP Moving information from the RDRAM onto the Channel (parallel word is muxed). Write (/precharge) command in COP field. Operation of modifying sense amp data. Extended opcode field in COLX packet INFINEON Technologies 92 2.00 |
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